I would imagine if you wanted to go to crazy bandwidths you could even use
optical transceivers on switches as single bit digitisers...

On Mon, 13 Nov 2023, 14:56 Dan Werthimer, <[email protected]> wrote:

>
> hi neil,
>
> paul horowitz, at harvard, had a PhD student who characterized and used
> FPGA LVDS inputs as ADC's for a seti experiment.
> that thesis is available, and i think there is a publication as well -
> paul will know.
>
> best wishes,
>
> dan
>
>
>
> On Mon, Nov 13, 2023 at 12:48 AM salmon.na via [email protected] <
> [email protected]> wrote:
>
>> Hi Dan,
>>
>>
>>
>> Just one further question, in terms of building a single bit
>> cross-correlator on an FPGA, exploiting differential LVDS pair for single
>> bit digitisation, might there be a suitable reference for this that I can
>> include in the paper and an IEEE transaction journal?
>>
>>
>>
>> Many thanks,
>>
>> Neil
>>
>>
>>
>> *From:* [email protected] <[email protected]> *On Behalf
>> Of *Dan Werthimer
>> *Sent:* 11 November 2023 21:52
>> *To:* [email protected]
>> *Subject:* Re: [casper] state of the art single bit correlators
>>
>>
>>
>>
>>
>> hi neil,
>>
>>
>>
>> i don't think waiting 5 years will help:
>>
>> there will be faster serdes - the current chips handle ~5 Tbit/sec and
>> that will probably double every two years,
>>
>> but that won't help you because you need other fpga's to convert your
>> slow 1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.
>>
>> and the fpga's will have more computing capability.
>>
>> but i don't think there will be more than 512 LVDS (low speed 1 Gsps)
>> inputs, as there's no market demand for that anymore.
>>
>> there are chips with much higher pin counts (CPUs have 4700 pins), and
>> would be easy for AMD or Intel to make an FPGA with more LVDS inputs,
>>
>> but there's no market.
>>
>>
>>
>> best wishes,
>>
>>
>>
>> dan
>>
>>
>>
>>
>>
>>
>>
>> Dan Werthimer
>>
>> Astronomy Dept and Space Sciences Lab
>>
>> University of California, Berkeley
>>
>>
>>
>>
>>
>> On Sat, Nov 11, 2023 at 1:39 PM salmon.na via [email protected] <
>> [email protected]> wrote:
>>
>> Hi Dan,
>>
>>
>>
>> Those are attractive looking numbers.
>>
>>
>>
>> Is it possible to say how that might scale over the next 5-years, will
>> the number of pins go up, faster than the processing speed, or the number
>> of gate on board? Is it likely to remain I/O bound of compute bound?
>>
>>
>>
>> Many thanks,
>>
>> Neil
>>
>>
>>
>> *From:* [email protected] <[email protected]> *On Behalf
>> Of *Dan Werthimer
>> *Sent:* 11 November 2023 21:30
>> *To:* [email protected]
>> *Subject:* Re: [casper] state of the art single bit correlators
>>
>>
>>
>>
>>
>> hi neil,
>>
>>
>>
>> for a single frequency channel correlator (continuum correlator), an XF
>> architecture (lag correlator) is the way to go,
>>
>> the number of antennas in your correlator will likely be limited by the
>> number of signals you can get into the FPGA.
>>
>> (the correlator will be I/O bound, not compute bound, assuming you have a
>> large FPGA).
>>
>>
>>
>> i haven't looked at the number of LVDS inputs available on a large FPGA
>> recently,
>>
>> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS
>> pairs (1024 pins).
>>
>> if so, you can have 512 digitizers, which is 256 complex digitizers,
>> which is 128 antennas dual pol, or 256 antenna single pol.
>>
>>
>>
>> as david hawkins suggested, could also use the high speed serdes on the
>> FPGA.
>>
>> the new pricy FPGAs have serdes that can work at >100 Gbps.
>>
>> and the larger pricy FPGAs have 32 of these serdes, which means you can
>> send 3.2 Tbits/sec into those FGPAs.
>>
>> that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams
>> at 1Gcomplexsamples/sec, or 800 antennas dual pol.
>>
>> but it would take a lot of electronics to convert 100 1Gbit/sec signals
>> into a 100Gbit/sec signal -
>>
>> the easiest way to convert 100 signals into a single 100Gsps signal would
>> be to use an FPGA,
>>
>> and that would defeat your goal of using a single FPGA for your
>> correlator.
>>
>>
>>
>>
>>
>> best wishes,
>>
>>
>>
>> dan
>>
>>
>>
>>
>>
>>
>>
>> On Sat, Nov 11, 2023 at 12:43 PM salmon.na via [email protected]
>> <[email protected]> wrote:
>>
>> Thanks Dan,
>>
>>
>>
>> Yes, one antenna for one receiver, and there is only one frequency
>> channel, and a single polarisation, so quite a simple configuration.
>>
>>
>>
>> A good idea to use differential inputs as single bit ADCs.
>>
>>
>>
>> So the FX correlator looks the better architecture.
>>
>>
>>
>> So are you saying the FPGA FX correlator would manage making the
>> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
>> FPGA, Xilinx or Altera ?
>>
>>
>>
>> Cheers,
>>
>> Neil
>>
>>
>>
>> *From:* [email protected] <[email protected]> *On Behalf
>> Of *Dan Werthimer
>> *Sent:* 11 November 2023 20:23
>> *To:* [email protected]
>> *Subject:* Re: [casper] state of the art single bit correlators
>>
>>
>>
>>
>>
>> hi neil,
>>
>>
>>
>> by number of receiver channels, i presume you mean number of antennas?
>>
>> are these single or dual polarization?
>>
>>
>>
>> how many spectral channels do you need in your correlator ?
>>
>>
>>
>> for a large number of spectral channels,
>>
>> you'll likely want to use an FX architecture correlator (not XF).
>>
>> in an FX correlator the number of ADC bits doesn't change the FPGA
>> utilization for the DSP very much.
>>
>>
>>
>> one fun thing you can do with a 1 bit correlator, is use the LVDS
>> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
>> with a lot of pins you can get about 512 ADC's
>>
>> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
>> digitizer and your correlator...
>>
>>
>>
>> if you only need a small number of spectral channels, you could build an
>> XF correlator
>>
>> with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single
>> pol) in a large FPGA.
>>
>>
>>
>> with an XF architecture, the FPGA utilization is  J  x
>> number_of_spectral_channels.
>>
>> for FX, the utilization goes as K  x  log_base_2(spectral_channels).
>>
>>
>>
>> but constant K >> constant J,
>>
>> so sometimes (rarely) it is better to use XF, depending on the number of
>> spectral channels.
>>
>>
>>
>>
>>
>> best wishes,
>>
>>
>>
>> dan
>>
>>
>>
>>
>>
>>
>>
>> On Sat, Nov 11, 2023 at 11:47 AM salmon.na via [email protected]
>> <[email protected]> wrote:
>>
>> For a paper on non-radioastronomy aperture synthesis technology I need to
>> know how many receiver channels can run into an almost top of the range
>> FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So
>> each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m
>> wondering if there are scaling laws for this and I only need to have a ball
>> park figure, ie a precision of say a factor of three or thereabouts. Any
>> associate papers related to that which might have clues to the capabilities
>> would be helpful.
>>
>>
>>
>> Many thanks,
>>
>> Neil Salmon
>>
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