Yes, Its my own design. I ask because when you run the synthesis and
implementation in Vivado it lets you continue and generate the bitstream
even if you have timing violations, so i think the casper tool could do the
same.

I have another question.. looking at the report my timing errors are
related to the adc_mmcm. Why does the system use an mmcm if the 125Mhz are
given by an external crystal and there is no modification to the frequency?
Its not enough to use a IBUFGDS?
Also I see a second mmcm named dsp_clk_mmcm feeded by the same adc clock, I
didnt look very carefully but guided by its name I assume it gives the
clock to the sysgen model. Why use a second clock, if its running at the
same frequency as the first mcmm?


El vie., 3 jul. 2020 a las 5:38, Jack Hickish (<[email protected]>)
escribió:

> This is probably a good conversation to have amongst the developers. ISE
> used to not deliver bitstreams unless you set an environment flag. I'm not
> sure it wouldn't make sense for the current toolflow to do the same.
>
> Timing failure warnings _are_ printed to the MATLAB prompt, but not in as
> shouty a way as they probably should be. I've tweaked them to be more
> obvious and this change will probably/hopefully be merged in the next major
> mlib_devel release.
>
> Cheers
> Jack
>
> On Fri, 3 Jul 2020, 8:51 am Adam Isaacson, <[email protected]> wrote:
>
>> Hi Sebastian,
>>
>> No, the timing analysis is performed during implementation - routing
>> phase and post routing optimisation phase. Bit generation occurs after this
>> - whether the design meets timing or not.
>>
>> Are you compiling tutorials or your own custom Red Pitaya design? The
>> tutorials should meet timing.
>>
>> Kind regards,
>>
>> Adam Isaacson
>> South African Radio Astronomy Observatory (SARAO)
>> Hardware Manager
>> Cell: (+27) 825639602
>> Tel:  (+27) 215067300
>> email: [email protected]
>>
>>
>>
>> On Fri, Jul 3, 2020 at 5:46 AM Sebastian Antonio Jorquera Tapia <
>> [email protected]> wrote:
>>
>>>
>>> Hello Casperites,
>>> Just a little question regarding the order of compilation.. I just
>>> compile a red pitaya design using the casper tool chain who generates the
>>> bitstream and says that the backend  is completed! But when I open the
>>> project with vivado I could see that the implementation had a time
>>> violation of 2.5ns in the setup time of signals related to the adc clock..
>>>
>>> So my question is, the time analysis is made after the bitstream are
>>> generated?
>>>
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