Hi Sebastian, No, the timing analysis is performed during implementation - routing phase and post routing optimisation phase. Bit generation occurs after this - whether the design meets timing or not.
Are you compiling tutorials or your own custom Red Pitaya design? The tutorials should meet timing. Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: [email protected] On Fri, Jul 3, 2020 at 5:46 AM Sebastian Antonio Jorquera Tapia < [email protected]> wrote: > > Hello Casperites, > Just a little question regarding the order of compilation.. I just compile > a red pitaya design using the casper tool chain who generates the bitstream > and says that the backend is completed! But when I open the project with > vivado I could see that the implementation had a time violation of 2.5ns in > the setup time of signals related to the adc clock.. > > So my question is, the time analysis is made after the bitstream are > generated? > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/4fb01928-987b-4d87-b62c-3ed40cd579f9n%40lists.berkeley.edu > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/4fb01928-987b-4d87-b62c-3ed40cd579f9n%40lists.berkeley.edu?utm_medium=email&utm_source=footer> > . > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CADTJ%3DnHjK6ELYzZgKCrou4-xUCEFS9svRkkWqFGUFV7abmYy6Q%40mail.gmail.com.
