Hi

I followed the tutorial and created the .slx file. While compiling I got 
these errors from simulink. 


Matching "From" for "Goto" 'rp_tut2/adc_in_snap/ss/goto_ss_we1' not found 
[4 similar]
Component:Simulink | Category:Block warning
Output port 1 of 'rp_tut2/dac/rp_tut2_dac_dac0_data_i_in' is not connected. 
[8 similar]
Component:Simulink | Category:Block warning
The input type propagated to this block did not match the specified type.
  Expected Type: Bool
  Actual Type: Fix_10_0

Error occurred during "Rate and Type Error Checking".


Reported by:
  'rp_tut2/adc_in_snap/assert_b'
A summary of Sysgen errors has been written to 
'/home/cet/RP_work/models/rp_tut2/rp_tut2_sysgen_error.log'

Reported by:
  'rp_tut2/adc_in_snap/assert_b'

I also notice that I do not get the "in_adc_data_valid" port shown in the 
in the bit field snap block on the tutorial page. Other than that, I 
recreated everything as mentioned in the tutorial page. I have attached the 
.slx  and the sysgen error log files also alongwith

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Attachment: rp_tut2.slx
Description: Binary data

--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 2019.1                 /opt/Xilinx/Vivado/2019.1
Matlab 9.4.0.813654 (R2018a)            /usr/local/MATLAB/R2018a
Vivado 2019.1                           /opt/Xilinx/Vivado/2019.1
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: Illegal data type
     Block: 'rp_tut2/adc/convert_adc_reset_in'
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  'rp_tut2/adc/convert_adc_reset_in'

Details:
The only arithmetic type that can be converted to a boolean is an
unsigned 1-bit integer --- i.e., a UFix_1_0.  For C-language
style translation of other types to booleans, use a Relational
block set to test for values not equal to zero.
Error occurred during "Rate and Type Error Checking".

--------------------------------------------------------------------------------

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