Hi Christian, > Hi wouldn't be better to ask tcc maintainers to support mfence for __i386 > target?
I don't see it as a bug if tcc/x86 assumes a target that does not support SSE instructions. "gcc -m32 -mno-sse" also assumes a target that does not support SSE instructions. Similarly, GCC/SPARC by default assumes only the SPARC v7 instruction set, although all SPARC CPUs made since 1993 support the SPARC v8+ instruction set. It's not a bug, just a choice made by the developers of the compiler. However, it would be useful if tcc/x86 had an option to enable and allow SSE instructions. In version 0.9.27, 'tcc -hh' does not list such an option. Bruno
