https://sourceware.org/bugzilla/show_bug.cgi?id=23647
Bug ID: 23647
Summary: ARM: Incorrect optimization of pseudo instruxtion ldr
rx,=0 for -mcpu=cortex-m0plus
Product: binutils
Version: 2.30
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: johan.dahlberg at electrumab dot se
Target Milestone: ---
Hello,
When the startup assembly code for the NXP S32K116 processor is assembled with
gas bundled with gcc versions 6 and 7, the "ldr rx,=0" pseudo instruction is
incorrectly optimized into an invalid instruction for this CPU, "mov.w rx,#0"
Source code:
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
...
Gas/Gcc version 6 and 7 generate the mov.w instruction, which does not exist
in the Cortex M0+ architecture.
Below is the disassembled code for gas/gcc version 7 (GNU assembler (GNU Tools
for Arm Embedded Processors 7-2018-q2-update) 2.30.0.20180329):
00000000 <Reset_Handler>:
0: b672 cpsid i
2: f04f 0100 mov.w r1, #0
6: f04f 0200 mov.w r2, #0
a: f04f 0300 mov.w r3, #0
Gas/Gcc version 5 correctly generates the movs instruction:
00000000 <Reset_Handler>:
0: b672 cpsid i
2: 2100 movs r1, #0
4: 2200 movs r2, #0
6: 2300 movs r3, #0
(As reference, the disassembled code for gas/gcc version 4.9, which
is less well optimized:
00000000 <Reset_Handler>:
0: b672 cpsid i
2: 4910 ldr r1, [pc, #64] ; (44 <JumpToSelf+0x2>)
4: 4a0f ldr r2, [pc, #60] ; (44 <JumpToSelf+0x2>)
6: 4b0f ldr r3, [pc, #60] ; (44 <JumpToSelf+0x2>)
)
Can you please fix this issue?
Meanwhile I stick with gas/gcc version 4 or 5...
Best regards,
/Johan Dahlberg
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