https://sourceware.org/bugzilla/show_bug.cgi?id=18500
--- Comment #7 from Alessandro Marzocchi <alessandro.marzocchi at gmail dot com> --- Hi Nick, thank for your patience. The latest patch should solve the problem indicated by you and match GNU coding standards (I hope at least). 2) I took that idea from ARM specs: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CJAEFGHE.html "VLDR pseudo-instruction The VLDR pseudo-instruction loads a constant value into every element of a 64-bit NEON vector, or into a VFP single-precision or double-precision register. [omissis] If an instruction (for example, VMOV) is available that can generate the constant directly into the register, the assembler uses it. Otherwise, it generates a doubleword literal pool entry containing the constant and loads the constant using a VLDR instruction." Also the conversion should not take more space (both VMOV and VLDR instruction get converted to 32 bit instruction in ARM and THUMB modes) while performing better (1 cycle vs 2/3 for Cortex M4). Regards Alessandro By the way... what is the correct way to load 1.0 in a double register? I tried this but it gives an error: .arm .syntax unified .fpu vfpv3 vmov d0,#0x3f800000 -- You are receiving this mail because: You are on the CC list for the bug. _______________________________________________ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
