I reported this some time ago, as part of a discussion at LHC. Since then, LHC 
Classic has run with two separate plan classes, one for sse3 and one for pni, 
with a bitwise-identical binary.

Plan class SSE3 works on most modern Intel CPUs, because the SSE3 string is 
found within the SSSE3 (triple-S) feature-set. But most AMD processors don't 
have the SSSE3 feature to match.

I think a single SSE3 plan_class should search for and match *either* sse3 *or* 
pni.



>________________________________
> From: David Anderson <[email protected]>
>To: Eric J Korpela <[email protected]> 
>Cc: Robert Kreß <[email protected]>; BOINC Dev Mailing List 
><[email protected]>; Boinc Projects <[email protected]> 
>Sent: Thursday, 8 August 2013, 18:43
>Subject: Re: [boinc_dev] SSE3 detection (Radim Van?o)
> 
>
>Hmm.  Our sample server-side code for an SSE3 plan class uses "sse3":
>
>     downcase_string(sreq.host.p_features);
>     if (!strstr(sreq.host.p_features, "sse3")) {
>
>Did this never work?
>Haven't some projects had SSE3 apps?
>Should I change it to "pni"?
>
>-- David
>
>On 08-Aug-2013 10:39 AM, Eric J Korpela wrote:
>> PNI is also the standard nomenclature on linux.    Unless something has
>> changed recently you won't see sse3 in /proc/cpuinfo .
>>
>>
>> On Thu, Aug 8, 2013 at 10:31 AM, Jorden van der Elst <[email protected]>wrote:
>>
>>> On Thu, Aug 8, 2013 at 7:09 PM, Robert Kreß <[email protected]> wrote:
>>>> Well Boinc is detecting SSE3 if it’s present and usable – but one called
>>> it
>>>> “pni” instead of SSE3 !?!
>>>
>>> Not 'one' called it that, but Intel themselves.
>>>
>>>  From http://en.wikipedia.org/wiki/SSE3
>>> "SSE3, Streaming SIMD Extensions 3, also known by its Intel code name
>>> Prescott New Instructions (PNI)"
>>>
>>>
>>>
>>> -- Jord van der Elst.
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