-------------- Original message -------------- 
From: "Peter St. John" <[EMAIL PROTECTED]> 

DLP? Wiki has entries for Indtruction Level Parallelism and Thread LP (alsom 
Memory LP) but 
not DLP?

Hey Peter,

That would be "data level parallelism".  So, ILP is very low level parallelism 
which
works on somewhat locally scoped instructions that are independent in a 
super-scalar, 
fanned-out parallel way on a "wide" processor.  TLP refers to a slightly higher 
level of parallelism
that is instruction dominated/oriented and is associated with independent 
program blocks
or loop interations (can be within or between programs or subroutines), and DLP 
refers
to data dominant parallelism usually associated with looping structures that 
could vectorize
or, in other words, allow a compiler to stimulate, with a small number of 
instructions, a large pipeline (and/or parallel stream [think GPUs here]) of 
independent data operations in the
CPU for which the total instruction latency is trivially small in theory (i.e. 
when you have a
vector instruction set).

In one sense, the low level parallelism (and structural hazard performance 
limitations) of any program can be defined by a sort of aspect ratio that is 
ILP x DLP x TLP and every code/kernel has its own dimensionality and volume. 

A major question for performance and processor design is also, which kind of 
latency dominates
--instruction latency or data latency--in limiting a code's performance to 
something less
than register-to-register optimal.  Generally, in  HPC data latency is dominant 
and the Enterprise world is instruction latency dominates.

But now I am probably rambling, and telling you something that you already know.

Regards,

rbw

-- 

"Making predictions is hard, especially about the future." 

Niels Bohr 

-- 

Richard Walsh 
Thrashing River Consulting-- 
5605 Alameda St. 
Shoreview, MN 55126 

Phone #: 612-382-4620
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