-------------- Original message --------------
From: "Finch, Ralph" <[EMAIL PROTECTED]>
> [I know nothing! Just copy-and-paste from a Usenet group]
>
> Subject: Tilera to Introduce 64-Core Processor
> Newsgroups: comp.arch, comp.arch.embedded, comp.sys.intel,
> alt.comp.hardware.amd.x86-64, comp.sys.ibm.pc.hardware.chips
> Date: Thu, 11 Oct 2007 11:02:14 -0700
>
It is cool, but not as cool as it could be ... it has no FPUs like the
development version or its academic predecessor, the RAW chip (or Intel's
Polaris, for that matter). But the on-chip interconnection network is
interesting and programmable, as is the pooled L3 cache. Eventually, as
Moore's Law scaling drives up core counts, this kind of programmable mesh
interconnect will replace what Intel and AMD currently provide. It a preview
of the "many core" future.
rbw
--
"Making predictions is hard, especially about the future."
Niels Bohr
--
Richard Walsh
Thrashing River Consulting--
5605 Alameda St.
Shoreview, MN 55126
Phone #: 612-382-4620
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