> What I was trying to say, if VS or HS change as the PCLK is rising, then 
> it may not register, but the next PCLK clock should register the VS or HS
>

Good point! In my case, the VS and HS signals are generated on the PCLK's 
falling edge though, so they should be valid on the next rising edge of the 
PCLK. I just measured again to verify. That being said, I also suspect the 
frame sync being off somehow and I've been exploring this possibility in 
detail and will continue to do so.

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