lol dahm text correction got me good that time "obstacle"

On Tue, May 16, 2017 at 1:26 AM, William Hermans <[email protected]> wrote:

>
>
> On Tue, May 16, 2017 at 1:07 AM, Joseph Heller <[email protected]
> > wrote:
>
>> On Tuesday, May 16, 2017 at 3:27:07 AM UTC+2, William Hermans wrote:
>>>
>>>
>>>
>>> On Wed, Apr 26, 2017 at 1:02 AM, Joseph Heller <[email protected]>
>>> wrote:
>>>
>>>> Updated link: http://catch22.eu/beaglebone/beaglebone-pru-c/
>>>>
>>>
>>> I may have mentioned this before, but I think blinking a USR LED would
>>> be far more useful. Nothing to hook up, and worry about blowing the pins on
>>> the processor, etc. However, then we're talking about involving the L3
>>> interconnect, which might be what you did not want to do ?
>>>
>>> A point of contention that I have with the article however, is: How does
>>> the GPIO bank + DATA_OUT register get into the PRU's _R30 register ? This
>>> also has to be dynamic somehow. I can't imagine all registers r0-r31 are
>>> each dedicated to a single control register of *something*. Then yes, I do
>>> know that some PRU registers are reserved, I just do not know which anymore.
>>>
>>
>> I don't know yet either at the moment. The way I use it in the example
>> seems to work magically per default. Risk is that is breaks though. An
>> explanation would be helpful.
>>
>
> Ah, ok, I was afraid of that. I do know the gpio registers fairly well, so
> maybe at some point I could figure that out. If I do I'll try to relay the
> info to you. One thing I'm thinking could be an obstetrical, is that there
> is GPIO that the PRU has direct access to, and then GPIO that has to be
> accessed over the L3 interconnect. Then I noticed from your article that
> the GPIO that you're using is mode 0x05, which is obviously PRU mux mode
> for GPO I suppose if you're controlling an LED. So yeah . . . will be a bit
> different.
>

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