On Thu, Oct 16, 2014 at 12:25 PM, Robert Nelson <[email protected]> wrote:
> On Thu, Oct 16, 2014 at 3:17 PM, Britton Kerin <[email protected]>
> wrote:
>> The SRM contains the following conflicting information:
>>
>> The System Reference Manual (SRM) says you're supposed to gate all GPIO
>> (and other inputs) such that they aren't driven until either the SYS_RESET
>> line goes high (according to SRM section 7.1, 8.0, and possibly others) or
>> until the VDD_3V3B rail is up (according to SRM 8.6.2). Are these conditions
>> identical in practice? If not which is the right one?
>>
>> Also, the reference manual section 8.3.1 says this:
>>
>> If you plan to use any of these signals, then on power up, these pins
>> should not be driven. If you do, it can affect the boot mode of the
>> processor and could keep the processor from booting or working
>> correctly.
>>
>> while not wrong this paragraph is going to create a dangerous wrong
>> impression
>> for most readers: that the boot pins are special and are the ones you have to
>> worry about driving early. I think it would be good to change this paragraph
>> or add a pointer to the other warnings that apply to all pins or something.
>
> Those pins control the bootrom's boot selection. If you drive them the
> wrong way after sys_reset you can change the processor to boot from an
> interface that isn't enable/setup/etc...
Ah, I understand. They can't be driven during boot. I was stuck on
the power issue.
It might be good to change section 8.3.1 to this:
If you plan to use any of these signals, then during boot, these pins
^^^^^^^^^^^
should not be driven. If you do, it can affect the boot mode of the
processor and could keep the processor from booting or working correctly.
"on power-up" changes to "during boot" or something.
Britton
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