> From: Hayk Martirosyan <[email protected]> > Date: Sat, 28 Feb 2026 20:02:37 +0400
Hi Hayk, > Hello, > > I'm trying to get the WAN network port working on the Radxa E20C board. > > The latest U-Boot release (v2026.01) doesn't support the port because > the board's DTB file lacks the required "pcie" and "combphy" > definitions. However, the DTB file from the "next" branch already > contains them. > > So I applied the following patch to the "next" branch, and I believe I > successfully built U-Boot with support for the port: > > --- a/configs/radxa-e20c-rk3528_defconfig > +++ b/configs/radxa-e20c-rk3528_defconfig > @@ -66,3 +66,8 @@ CONFIG_USB_GADGET=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_USB_FUNCTION_ROCKUSB=y > CONFIG_ERRNO_STR=y > +CONFIG_PCIE_DW_ROCKCHIP=y > +CONFIG_PCI=y > +CONFIG_CMD_PCI=y > +CONFIG_BOOTDELAY=15 > +CONFIG_RTL8169=y > > To activate the port, I interrupt the boot process and manually run the > "pci enum" command. The output of the subsequent "pci long" command > looks fine (see below). > > OpenBSD boots successfully after that, and ifconfig shows two NICs. > However, I cannot get the second NIC to work. The command "ifconfig > re0 up autoconf" appears to succeed, but the NIC never obtains an IPv4 > address via DHCP. Instead, the message "re0: watchdog timeout" starts > appearing on the console repeatedly. > > My guess is that OpenBSD currently lacks some RK3528/PCIe-related > support. For example, there are no mentions of rockchip,rk3528-pcie in > src/sys/dev/fdt/dwpcie.c. However, I may be completely wrong, so I would > appreciate it if someone could validate this assumption. I'd also be > happy to test any patches if someone is willing to help get this > working. I don't have any RK3528 hardware myself. But your dmesg shows a few potential issues: > > Below is the full boot log and the commands I ran: > > DDR V1.05 2eef4a672d huan.he 23/04/14-10:57:28 > LP4/4x derate disable, other dram:1x trefi > ddrconfig:7 > LP4 MR14:0x4d > LPDDR4, 324MHz > BW=32 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=4096MB > tdqss: cs0 dqs0: 554ps, dqs1: 482ps, dqs2: 602ps, dqs3: 530ps, > tdqss: cs1 dqs0: 554ps, dqs1: 482ps, dqs2: 578ps, dqs3: 530ps, > > change to: 324MHz > clk skew:0x58 > > change to: 528MHz > clk skew:0x66 > > change to: 780MHz > clk skew:0x58 > > change to: 1056MHz(final freq) > PHY drv:clk:49,ca:49,DQ:40,odt:80 > vrefinner:19%, vrefout:31% > dram drv:40,odt:60 > vref_ca:0000005E > clk skew:0x1b > cs 0: > the read training result: > DQS0:0x40, DQS1:0x45, DQS2:0x40, DQS3:0x3f, > min : 0x9 0xc 0xe 0xd 0x8 0x2 0x5 0x6 , 0xf 0xe 0x5 0x1 0x8 0x11 > 0xa 0x9 , > 0xd 0xe 0xe 0xe 0x7 0x2 0xa 0x6 , 0xb 0x2 0x5 0x4 0x5 0xe > 0xc 0x8 , > mid :0x24 0x26 0x28 0x27 0x23 0x1d 0x1e 0x1f ,0x29 0x28 0x1d 0x1b 0x23 0x2d > 0x23 0x22 , > 0x26 0x28 0x29 0x28 0x21 0x1b 0x23 0x1f ,0x23 0x1c 0x1f 0x1d 0x1e 0x26 > 0x23 0x21 , > max :0x40 0x41 0x42 0x41 0x3f 0x39 0x38 0x39 ,0x43 0x43 0x36 0x35 0x3e 0x49 > 0x3d 0x3b , > 0x3f 0x43 0x44 0x42 0x3b 0x34 0x3d 0x39 ,0x3c 0x36 0x3a 0x36 0x38 0x3f > 0x3b 0x3a , > range:0x37 0x35 0x34 0x34 0x37 0x37 0x33 0x33 ,0x34 0x35 0x31 0x34 0x36 0x38 > 0x33 0x32 , > 0x32 0x35 0x36 0x34 0x34 0x32 0x33 0x33 ,0x31 0x34 0x35 0x32 0x33 0x31 > 0x2f 0x32 , > the write training result: > DQS0:0x65, DQS1:0x5c, DQS2:0x6c, DQS3:0x62, > min :0x96 0x96 0x99 0x98 0x93 0x8b 0x8f 0x8f 0x92 ,0x8c 0x8a 0x7e 0x7c 0x83 > 0x8a 0x83 0x84 0x8b , > 0x9a 0x99 0x99 0x98 0x90 0x88 0x93 0x90 0x95 ,0x8c 0x83 0x87 0x84 0x85 > 0x8a 0x8b 0x88 0x86 , > mid :0xad 0xac 0xae 0xab 0xa7 0xa0 0xa1 0xa1 0xa8 ,0xa2 0xa0 0x92 0x8d 0x9a > 0xa1 0x97 0x97 0xa1 , > 0xaf 0xaf 0xae 0xac 0xa4 0x9d 0xa9 0xa4 0xaa ,0xa3 0x99 0x9d 0x9a 0x9b > 0xa1 0x9e 0x9c 0x9c , > max :0xc4 0xc2 0xc3 0xbf 0xbb 0xb6 0xb3 0xb4 0xbe ,0xb8 0xb6 0xa6 0x9f 0xb1 > 0xb8 0xac 0xaa 0xb8 , > 0xc4 0xc6 0xc3 0xc1 0xb9 0xb2 0xbf 0xb9 0xbf ,0xba 0xaf 0xb4 0xb1 0xb2 > 0xb9 0xb2 0xb0 0xb2 , > range:0x2e 0x2c 0x2a 0x27 0x28 0x2b 0x24 0x25 0x2c ,0x2c 0x2c 0x28 0x23 0x2e > 0x2e 0x29 0x26 0x2d , > 0x2a 0x2d 0x2a 0x29 0x29 0x2a 0x2c 0x29 0x2a ,0x2e 0x2c 0x2d 0x2d 0x2d > 0x2f 0x27 0x28 0x2c , > cs 1: > the read training result: > DQS0:0x40, DQS1:0x44, DQS2:0x40, DQS3:0x40, > min : 0x8 0xb 0xc 0xb 0x8 0x1 0x2 0x2 , 0xd 0xd 0x4 0x1 0x5 0x10 > 0x6 0x7 , > 0xd 0xe 0xd 0xe 0x8 0x2 0xa 0x6 , 0x9 0x1 0x5 0x2 0x4 0xc > 0xa 0x7 , > mid :0x24 0x26 0x27 0x26 0x24 0x1d 0x1d 0x1d ,0x27 0x28 0x1d 0x1a 0x21 0x2c > 0x21 0x1f , > 0x27 0x29 0x28 0x28 0x22 0x1b 0x24 0x1f ,0x24 0x1d 0x20 0x1d 0x1f 0x26 > 0x23 0x21 , > max :0x40 0x42 0x43 0x42 0x40 0x3a 0x39 0x39 ,0x42 0x43 0x36 0x34 0x3d 0x48 > 0x3c 0x38 , > 0x41 0x44 0x44 0x42 0x3c 0x34 0x3e 0x39 ,0x3f 0x39 0x3c 0x39 0x3b 0x40 > 0x3d 0x3b , > range:0x38 0x37 0x37 0x37 0x38 0x39 0x37 0x37 ,0x35 0x36 0x32 0x33 0x38 0x38 > 0x36 0x31 , > 0x34 0x36 0x37 0x34 0x34 0x32 0x34 0x33 ,0x36 0x38 0x37 0x37 0x37 0x34 > 0x33 0x34 , > the write training result: > DQS0:0x65, DQS1:0x5c, DQS2:0x6c, DQS3:0x62, > min :0x94 0x94 0x97 0x95 0x91 0x89 0x8d 0x8d 0x90 ,0x88 0x87 0x7b 0x78 0x81 > 0x88 0x80 0x81 0x88 , > 0x9e 0x9d 0x9e 0x9c 0x95 0x8f 0x98 0x95 0x99 ,0x92 0x88 0x8d 0x8a 0x8b > 0x91 0x91 0x8f 0x8b , > mid :0xaa 0xa9 0xab 0xa8 0xa4 0x9d 0x9e 0x9f 0xa5 ,0x9e 0x9d 0x8f 0x8a 0x97 > 0x9e 0x95 0x94 0x9e , > 0xb4 0xb4 0xb3 0xb1 0xa9 0xa3 0xad 0xa9 0xae ,0xaa 0xa0 0xa4 0xa1 0xa2 > 0xa8 0xa5 0xa4 0xa2 , > max :0xc0 0xbf 0xbf 0xbc 0xb8 0xb2 0xb0 0xb2 0xbb ,0xb5 0xb3 0xa3 0x9d 0xae > 0xb5 0xaa 0xa8 0xb5 , > 0xcb 0xcb 0xc8 0xc6 0xbe 0xb8 0xc3 0xbd 0xc4 ,0xc2 0xb8 0xbc 0xb9 0xba > 0xc0 0xba 0xb9 0xba , > range:0x2c 0x2b 0x28 0x27 0x27 0x29 0x23 0x25 0x2b ,0x2d 0x2c 0x28 0x25 0x2d > 0x2d 0x2a 0x27 0x2d , > 0x2d 0x2e 0x2a 0x2a 0x29 0x29 0x2b 0x28 0x2b ,0x30 0x30 0x2f 0x2f 0x2f > 0x2f 0x29 0x2a 0x2f , > CA Training result: > cs:0 min :0x43 0x43 0x50 0x4d 0x47 0x4a 0x41 ,0x3b 0x3d 0x3a 0x41 0x43 0x43 > 0x36 , > cs:0 mid :0x7c 0x7b 0x8a 0x87 0x80 0x84 0x6b ,0x75 0x75 0x73 0x7a 0x7b 0x7b > 0x66 , > cs:0 max :0xb5 0xb3 0xc4 0xc1 0xb9 0xbf 0x96 ,0xaf 0xae 0xac 0xb4 0xb4 0xb4 > 0x96 , > cs:0 range:0x72 0x70 0x74 0x74 0x72 0x75 0x55 ,0x74 0x71 0x72 0x73 0x71 0x71 > 0x60 , > cs:1 min :0x45 0x47 0x54 0x50 0x4a 0x4b 0x3f ,0x40 0x40 0x3e 0x44 0x45 0x43 > 0x35 , > cs:1 mid :0x7e 0x7f 0x8d 0x8a 0x81 0x86 0x6a ,0x79 0x79 0x76 0x7d 0x7e 0x7e > 0x65 , > cs:1 max :0xb8 0xb7 0xc6 0xc5 0xb9 0xc2 0x95 ,0xb2 0xb3 0xae 0xb7 0xb8 0xba > 0x95 , > cs:1 range:0x73 0x70 0x72 0x75 0x6f 0x77 0x56 ,0x72 0x73 0x70 0x73 0x73 0x77 > 0x60 , > out > U-Boot SPL board init > U-Boot SPL 2017.09-OpenWrt-2024062614 (Jun 26 2024 - 06:57:14) > Trying to boot from MMC2 > Trying fit image at 0x4000 sector > ## Verified-boot: 0 > ## Checking atf-1 0x00080000 ... sha256(8188d27a43...) + OK > ## Checking u-boot 0x00800000 ... sha256(443f6390ff...) + OK > ## Checking fdt-1 0x008d58b0 ... sha256(c2b198a2b5...) + OK > ## Checking atf-2 0xfe48d000 ... sha256(d387809e05...) + OK > ## Checking atf-3 0xfe490000 ... sha256(a23cc2a6ff...) + OK > Jumping to U-Boot(0x00800000) via ARM Trusted Firmware(0x00080000) > Total: 312.486/387.211 ms > > INFO: Preloader serial: 0 > NOTICE: BL31: v2.3():v2.3-912-gfe961b77f:derrick.huang, fwver: v1.20 > NOTICE: BL31: Built : 16:59:19, Mar 31 2025 > INFO: rk_otp_init finish! > INFO: code: 0x28 > INFO: ARM GICv2 driver initialized > INFO: nonboot_cpus_off: clst_st=0xc0e, core_st=0xe1e0 boot_cpu=0 > INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz > INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz > INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz > INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz > INFO: idle_st=0x0, pd_st=0x0 > INFO: Using opteed sec cpu_context! > INFO: boot cpu mask: 1 > INFO: RK3528 SoC (0x101) > INFO: BL31: Initializing runtime services > WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE > initialization. SMC`s destined for OPTEE will return SMC_UNK > ERROR: Error initializing runtime service opteed_fast > INFO: BL31: Preparing for EL3 exit to normal world > INFO: Entry point address = 0x800000 > INFO: SPSR = 0x3c9 > > U-Boot 2026.04-rc3-00127-gf6963fc23260-dirty (Feb 28 2026 - 19:09:42 +0400) > > Model: Radxa E20C > SoC: RK3528A > DRAM: 4 GiB (total 3.9 GiB) > Core: 374 devices, 30 uclasses, devicetree: separate > MMC: mmc@ffbf0000: 0, mmc@ffc30000: 1 > Loading Environment from nowhere... OK > In: serial@ff9f0000 > Out: serial@ff9f0000 > Err: serial@ff9f0000 > Net: eth0: ethernet@ffbe0000 > Hit any key to stop autoboot: 0 > => pci enum > => pci long > > Found PCI device 00.00.00: > vendor ID = 0x1d87 > device ID = 0x3528 > command register ID = 0x0107 > status register = 0x0010 > revision ID = 0x01 > class code = 0x06 (Bridge device) > sub class code = 0x04 > programming interface = 0x00 > cache line = 0x08 > latency time = 0x00 > header type = 0x01 > BIST = 0x00 > base address 0 = 0x00000000 > base address 1 = 0x00000000 > primary bus number = 0x00 > secondary bus number = 0x01 > subordinate bus number = 0x01 > secondary latency timer = 0x00 > IO base = 0x00 > IO limit = 0x00 > secondary status = 0x0000 > memory base = 0xfc20 > memory limit = 0xfc20 > prefetch memory base = 0xfff1 > prefetch memory limit = 0x0001 > prefetch memory base upper = 0x00000000 > prefetch memory limit upper = 0x00000000 > IO base upper 16 bits = 0x0000 > IO limit upper 16 bits = 0x0000 > expansion ROM base address = 0x00000000 > interrupt line = 0xff > interrupt pin = 0x01 > bridge control = 0x0000 > > Found PCI device 01.00.00: > vendor ID = 0x10ec > device ID = 0x8168 > command register ID = 0x0007 > status register = 0x0010 > revision ID = 0x15 > class code = 0x02 (Network controller) > sub class code = 0x00 > programming interface = 0x00 > cache line = 0x08 > latency time = 0x00 > header type = 0x00 > BIST = 0x00 > base address 0 = 0xfc100001 > base address 1 = 0x00000000 > base address 2 = 0xfc200004 > base address 3 = 0x00000000 > base address 4 = 0xfc204004 > base address 5 = 0x00000000 > cardBus CIS pointer = 0x00000000 > sub system vendor ID = 0x10ec > sub system ID = 0x0123 > expansion ROM base address = 0x00000000 > interrupt line = 0xff > interrupt pin = 0x01 > min Grant = 0x00 > max Latency = 0x00 > => boot > Scanning for bootflows in all bootdevs > Seq Method State Uclass Part Name Filename > --- ----------- ------ -------- ---- ------------------------ - > --------------- > Scanning global bootmeth 'efi_mgr': > Cannot persist EFI variables without system partition > 0 efi_mgr ready (none) 0 <NULL> > ** Booting bootflow '<NULL>' with efi_mgr > Loading Boot0000 'mmc 0' failed > Booting: Label: mmc 1 Device path: /VenHw > (e61d73b9-a384-4acc-aeab-82e828f3628b,0000000000000000)/VenHw > (e61d73b9-a384-4acc-aeab-82e828f3628b,7200000000000000)/SD(1)/SD(1) > disks: sd0* sd1 > >> OpenBSD/arm64 BOOTAA64 1.22 > boot> > cannot open sd0a:/etc/random.seed: No such file or directory > booting sd0a:/bsd: 3061308+1283676+12718640+646240 > [268894+91+726408+294645]=0x13fa0d0 > Copyright (c) 1982, 1986, 1989, 1991, 1993 > The Regents of the University of California. All rights reserved. > Copyright (c) 1995-2025 OpenBSD. All rights reserved. > https://www.OpenBSD.org > > OpenBSD 7.8 (RAMDISK) #38: Sun Oct 12 18:49:37 MDT 2025 > [email protected]:/usr/src/sys/arch/arm64/compile/RAMDISK > real mem = 4223954944 (4028MB) > avail mem = 4008341504 (3822MB) > random: good seed from bootblocks > mainbus0 at root: Radxa E20C > psci0 at mainbus0: PSCI 1.1, SMCCC 1.2, SYSTEM_SUSPEND > efi0 at mainbus0: UEFI 2.11 > efi0: Das U-Boot rev 0x20260400 > smbios0 at efi0: SMBIOS 3.7.0 > smbios0: vendor U-Boot version "2026.04-rc3-00127-gf6963fc23260-dirty" date > 04/01/2026 > smbios0: radxa Radxa E20C > cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4 > cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache > cpu0: 256KB 64b/line 16-way L2 cache > cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16 > scmi0 at mainbus0: SCMI 2.0 > "shmem" at mainbus0 not configured > rkpinctrl0 at mainbus0: no registers This is a problem. But committed a potential solution for this a few days ago. It is worth retrying with a recent snapshot, or a -current kernel you built yourself. > "fit-images" at mainbus0 not configured > "firmware" at mainbus0 not configured > "opp-table-cpu" at mainbus0 not configured > "opp-table-gpu" at mainbus0 not configured > agtimer0 at mainbus0: 24000 kHz > "clock-xin24m" at mainbus0 not configured > "clock-gmac50m" at mainbus0 not configured > simplebus0 at mainbus0: "soc" > ampintc0 at simplebus0 nirq 224, ncpu 4: "interrupt-controller" > syscon0 at simplebus0: "qos" > syscon1 at simplebus0: "qos" > syscon2 at simplebus0: "qos" > syscon3 at simplebus0: "qos" > syscon4 at simplebus0: "qos" > syscon5 at simplebus0: "qos" > syscon6 at simplebus0: "qos" > syscon7 at simplebus0: "qos" > syscon8 at simplebus0: "qos" > syscon9 at simplebus0: "qos" > syscon10 at simplebus0: "qos" > syscon11 at simplebus0: "qos" > syscon12 at simplebus0: "qos" > syscon13 at simplebus0: "qos" > syscon14 at simplebus0: "qos" > syscon15 at simplebus0: "qos" > syscon16 at simplebus0: "qos" > syscon17 at simplebus0: "qos" > syscon18 at simplebus0: "qos" > syscon19 at simplebus0: "qos" > syscon20 at simplebus0: "qos" > syscon21 at simplebus0: "qos" > syscon22 at simplebus0: "qos" > syscon23 at simplebus0: "qos" > syscon24 at simplebus0: "qos" > syscon25 at simplebus0: "qos" > syscon26 at simplebus0: "qos" > syscon27 at simplebus0: "qos" > syscon28 at simplebus0: "qos" > syscon29 at simplebus0: "qos" > syscon30 at simplebus0: "qos" > syscon31 at simplebus0: "qos" > syscon32 at simplebus0: "syscon" > syscon33 at simplebus0: "syscon" > syscon34 at simplebus0: "syscon" > rkclock0 at simplebus0 > rkclock_set_frequency(rkclock0, 372, 32768) > rkclock_set_frequency(rkclock0, 2, 1188000000) > rkclock_set_frequency(rkclock0, 3, 1000000000) > rkclock_set_frequency(rkclock0, 1, 996000000) > rkclock_set_frequency(rkclock0, 5, 408000000) > rkclock_set_frequency(rkclock0, 11, 250000000) > rkclock_set_frequency(rkclock0, 15, 500000000) > rkclock_set_frequency(rkclock0, 9, 150000000) > rkclock_set_frequency(rkclock0, 12, 300000000) > rkclock_set_frequency(rkclock0, 13, 340000000) > rkclock_set_frequency(rkclock0, 14, 400000000) > rkclock_set_frequency(rkclock0, 16, 600000000) > rkclock_set_frequency(rkclock0, 122, 50000000) > rkclock_set_frequency(rkclock0, 121, 100000000) > rkclock_set_frequency(rkclock0, 76, 500000000) This means there clocks missing in the rkclock(4) driver. I'll see if I can find some time to add them. > syscon35 at simplebus0: "syscon" > syscon36 at simplebus0: "power-management" > "power-controller" at syscon36 not configured > dwpcie0 at simplebus0 > "gpu" at simplebus0 not configured > com0 at simplebus0: dw16550, 64 byte fifo > com0: console > rkiic0 at simplebus0 > iic0 at rkiic0 > "belling,bl24c16a" at iic0 addr 0x50 not configured > rkpwm0 at simplebus0 > rkpwm1 at simplebus0 > "adc" at simplebus0 not configured > dwqe0 at simplebus0 gmac 1: rev 0x51, address 22:22:22:22:22:22 > ytphy0 at dwqe0 phy 1: YT8531, rev. 11 > dwmshc0 at simplebus0 > dwmshc0: SDHC 4.20, 200 MHz base clock > sdmmc0 at dwmshc0: 8-bit, sd high-speed, mmc high-speed, dma > dwmmc0 at simplebus0: 49 MHz base clock > sdmmc1 at dwmmc0: 4-bit, sd high-speed, mmc high-speed, dma > "dma-controller" at simplebus0 not configured > "phy" at simplebus0 not configured > "rng" at simplebus0 not configured > "nvmem" at simplebus0 not configured > rk3528_reset: 0x00000064 > rk3528_reset: 0x00000062 > rk3528_reset: 0x00000064 > rk3528_reset: 0x00000062 Some resets missing as well from rkclock(4). > pci0 at dwpcie0 > ppb0 at pci0 dev 0 function 0 vendor "Rockchip", unknown product 0x3528 rev > 0x00 > pci1 at ppb0 bus 1 > re0 at pci1 dev 0 function 0 "Realtek 8168" rev 0x15: RTL8168H/8111H > (0x5400), intx, address 11:11:11:11:11:11 > rgephy0 at re0 phy 7: RTL8251, rev. 0 > "adc-keys" at mainbus0 not configured > "gpio-keys" at mainbus0 not configured > "leds" at mainbus0 not configured > "regulator-0v9-vdd" at mainbus0 not configured > "regulator-1v1-vcc-ddr" at mainbus0 not configured > "regulator-1v8-vcc" at mainbus0 not configured > "regulator-3v3-vcc" at mainbus0 not configured > "regulator-5v0-vcc-sys" at mainbus0 not configured > "regulator-vccio-sd" at mainbus0 not configured > "regulator-vdd-arm" at mainbus0 not configured > "regulator-vdd-logic" at mainbus0 not configured > "binman" at mainbus0 not configured > "dmc" at mainbus0 not configured > scsibus0 at sdmmc0: 2 targets, initiator 0 > sd0 at scsibus0 targ 1 lun 0: <SD/MMC, TLimmc, 0000> > sd0: 30056MB, 512 bytes/sector, 61554688 sectors > scsibus1 at sdmmc1: 2 targets, initiator 0 > sd1 at scsibus1 targ 1 lun 0: <SD/MMC, JC1S5, 0030> removable > sd1: 61120MB, 512 bytes/sector, 125173760 sectors > softraid0 at root > scsibus2 at softraid0: 256 targets > root on rd0a swap on rd0b dump on rd0b > WARNING: CHECK AND RESET THE DATE! > cpu0: regulator not implemented > erase ^?, werase ^W, kill ^U, intr ^C, status ^T > > Welcome to the OpenBSD/arm64 7.8 installation program. > (I)nstall, (U)pgrade, (A)utoinstall or (S)hell? s > # ifconfig > > lo0: flags=2008008<LOOPBACK,MULTICAST,LRO> mtu 32768 > llprio 3 > groups: lo > dwqe0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500 > lladdr 22:22:22:22:22:22 > llprio 3 > media: Ethernet autoselect > status: unknown > re0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500 > lladdr 11:11:11:11:11:11 > llprio 3 > media: Ethernet autoselect (none) > status: unknown > # ifconfig re0 up autoconf > > # re0: watchdog timeout > # ifconfig > > lo0: flags=2008008<LOOPBACK,MULTICAST,LRO> mtu 32768 > llprio 3 > groups: lo > dwqe0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500 > lladdr 22:22:22:22:22:22 > llprio 3 > media: Ethernet autoselect > status: no carrier > re0: flags=808843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST,AUTOCONF4> mtu 1500 > lladdr 11:11:11:11:11:11 > llprio 3 > media: Ethernet autoselect (1000baseT full-duplex,rxpause,txpause) > status: active This actually suggests that the PCIe controller is (mostly) working. > # re0: watchdog timeout > re0: watchdog timeout > re0: watchdog timeout > re0: watchdog timeout > re0: watchdog timeout > re0: watchdog timeout > ... The following bootloader diff might help. I'll probably going to get this committed quickly. Index: arch/arm64/stand/efiboot/efiboot.c =================================================================== RCS file: /cvs/src/sys/arch/arm64/stand/efiboot/efiboot.c,v diff -u -p -r1.68 efiboot.c --- arch/arm64/stand/efiboot/efiboot.c 25 Jan 2026 18:19:13 -0000 1.68 +++ arch/arm64/stand/efiboot/efiboot.c 9 Mar 2026 20:16:55 -0000 @@ -601,7 +601,8 @@ efi_dma_constraint(void) node = fdt_find_node("/"); if (fdt_node_is_compatible(node, "brcm,bcm2711")) dma_constraint[1] = htobe64(0x3bffffff); - if (fdt_node_is_compatible(node, "rockchip,rk3566") || + if (fdt_node_is_compatible(node, "rockchip,rk3528") || + fdt_node_is_compatible(node, "rockchip,rk3566") || fdt_node_is_compatible(node, "rockchip,rk3568") || fdt_node_is_compatible(node, "rockchip,rk3588") || fdt_node_is_compatible(node, "rockchip,rk3588s"))
