On 2022-06-03 14:50, Rodrigo Siqueira wrote: > GCC throw warnings for the function dcn31_update_bw_bounding_box and > dcn316_update_bw_bounding_box due to its frame size that looks like > this: > > error: the frame size of 1936 bytes is larger than 1024 bytes > [-Werror=frame-larger-than=] > > For fixing this issue I dropped an intermadiate variable. > > Cc: Stephen Rothwell <[email protected]> > Cc: Hamza Mahfooz <[email protected]> > Cc: Aurabindo Pillai <[email protected]> > Signed-off-by: Rodrigo Siqueira <[email protected]>
Reviewed-by: Harry Wentland <[email protected]> Harry > --- > .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 +++++++++---------- > 1 file changed, 26 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > index 54db2eca9e6b..ee898bc93fd5 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > @@ -574,7 +574,6 @@ void dcn31_calculate_wm_and_dlg_fp( > void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params > *bw_params) > { > struct clk_limit_table *clk_table = &bw_params->clk_table; > - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; > unsigned int i, closest_clk_lvl; > int j; > > @@ -607,29 +606,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct > clk_bw_params *bw_params > } > } > > - clock_limits[i].state = i; > + dcn3_1_soc.clock_limits[i].state = i; > > /* Clocks dependent on voltage level. */ > - clock_limits[i].dcfclk_mhz = > clk_table->entries[i].dcfclk_mhz; > - clock_limits[i].fabricclk_mhz = > clk_table->entries[i].fclk_mhz; > - clock_limits[i].socclk_mhz = > clk_table->entries[i].socclk_mhz; > - clock_limits[i].dram_speed_mts = > clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; > + dcn3_1_soc.clock_limits[i].dcfclk_mhz = > clk_table->entries[i].dcfclk_mhz; > + dcn3_1_soc.clock_limits[i].fabricclk_mhz = > clk_table->entries[i].fclk_mhz; > + dcn3_1_soc.clock_limits[i].socclk_mhz = > clk_table->entries[i].socclk_mhz; > + dcn3_1_soc.clock_limits[i].dram_speed_mts = > clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; > > /* Clocks independent of voltage level. */ > - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? > max_dispclk_mhz : > + dcn3_1_soc.clock_limits[i].dispclk_mhz = > max_dispclk_mhz ? max_dispclk_mhz : > > dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; > > - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? > max_dppclk_mhz : > + dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz > ? max_dppclk_mhz : > > dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; > > - clock_limits[i].dram_bw_per_chan_gbps = > dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; > - clock_limits[i].dscclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; > - clock_limits[i].dtbclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; > - clock_limits[i].phyclk_d18_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; > - clock_limits[i].phyclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; > + dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = > dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; > + dcn3_1_soc.clock_limits[i].dscclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; > + dcn3_1_soc.clock_limits[i].dtbclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; > + dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; > + dcn3_1_soc.clock_limits[i].phyclk_mhz = > dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; > } > - for (i = 0; i < clk_table->num_entries; i++) > - dcn3_1_soc.clock_limits[i] = clock_limits[i]; > if (clk_table->num_entries) { > dcn3_1_soc.num_states = clk_table->num_entries; > } > @@ -701,7 +698,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct > clk_bw_params *bw_param > void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params > *bw_params) > { > struct clk_limit_table *clk_table = &bw_params->clk_table; > - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; > unsigned int i, closest_clk_lvl; > int max_dispclk_mhz = 0, max_dppclk_mhz = 0; > int j; > @@ -739,34 +735,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, > struct clk_bw_params *bw_param > closest_clk_lvl = dcn3_16_soc.num_states - 1; > } > > - clock_limits[i].state = i; > + dcn3_16_soc.clock_limits[i].state = i; > > /* Clocks dependent on voltage level. */ > - clock_limits[i].dcfclk_mhz = > clk_table->entries[i].dcfclk_mhz; > + dcn3_16_soc.clock_limits[i].dcfclk_mhz = > clk_table->entries[i].dcfclk_mhz; > if (clk_table->num_entries == 1 && > - clock_limits[i].dcfclk_mhz < > dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { > + dcn3_16_soc.clock_limits[i].dcfclk_mhz < > dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { > /*SMU fix not released yet*/ > - clock_limits[i].dcfclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; > + dcn3_16_soc.clock_limits[i].dcfclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; > } > - clock_limits[i].fabricclk_mhz = > clk_table->entries[i].fclk_mhz; > - clock_limits[i].socclk_mhz = > clk_table->entries[i].socclk_mhz; > - clock_limits[i].dram_speed_mts = > clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; > + dcn3_16_soc.clock_limits[i].fabricclk_mhz = > clk_table->entries[i].fclk_mhz; > + dcn3_16_soc.clock_limits[i].socclk_mhz = > clk_table->entries[i].socclk_mhz; > + dcn3_16_soc.clock_limits[i].dram_speed_mts = > clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; > > /* Clocks independent of voltage level. */ > - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? > max_dispclk_mhz : > + dcn3_16_soc.clock_limits[i].dispclk_mhz = > max_dispclk_mhz ? max_dispclk_mhz : > > dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; > > - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? > max_dppclk_mhz : > + dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz > ? max_dppclk_mhz : > > dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; > > - clock_limits[i].dram_bw_per_chan_gbps = > dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; > - clock_limits[i].dscclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; > - clock_limits[i].dtbclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; > - clock_limits[i].phyclk_d18_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; > - clock_limits[i].phyclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; > + dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = > dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; > + dcn3_16_soc.clock_limits[i].dscclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz; > + dcn3_16_soc.clock_limits[i].dtbclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; > + dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; > + dcn3_16_soc.clock_limits[i].phyclk_mhz = > dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz; > } > - for (i = 0; i < clk_table->num_entries; i++) > - dcn3_16_soc.clock_limits[i] = clock_limits[i]; > if (clk_table->num_entries) { > dcn3_16_soc.num_states = clk_table->num_entries; > }
