The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14.
Change-Id: I8be4256079f81e292b39bcf43b4a84db82aa069b Signed-off-by: Evan Quan <[email protected]> --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index e02d036fb298..801c92eb439f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2185,19 +2185,18 @@ static int navi10_run_btc(struct smu_context *smu) return ret; } -static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev) +static bool navi10_need_umc_cdr_12gbps_workaround(struct smu_context *smu) { - if (adev->asic_type != CHIP_NAVI10) + struct amdgpu_device *adev = smu->adev; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) return false; - if (adev->pdev->device == 0x731f && - (adev->pdev->revision == 0xc2 || - adev->pdev->revision == 0xc3 || - adev->pdev->revision == 0xca || - adev->pdev->revision == 0xcb)) + if (adev->asic_type == CHIP_NAVI10 || + adev->asic_type == CHIP_NAVI14) return true; - else - return false; + + return false; } static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) @@ -2285,7 +2284,7 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu) uint32_t param; int ret = 0; - if (!navi10_need_umc_cdr_12gbps_workaround(adev)) + if (!navi10_need_umc_cdr_12gbps_workaround(smu)) return 0; ret = smu_cmn_send_smc_msg_with_param(smu, -- 2.28.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
