And different workaround will be applied based on hybrid cdr bit.
Change-Id: I828dc3605dbe0bb5a5e1a0db409658608ff21888
Signed-off-by: Evan Quan <[email protected]>
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h | 4 ++-
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 28 +++++++++++++++----
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 4a8655a20ef6..35fc46d3c9c0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -175,6 +175,7 @@
__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
+ __SMU_DUMMY_MAP(GET_UMC_FW_WA), \
__SMU_DUMMY_MAP(Mode1Reset), \
#undef __SMU_DUMMY_MAP
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h
index fc8594e9b2bd..26181b679098 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h
@@ -128,7 +128,9 @@
#define PPSMC_MSG_SetDriverDummyTableDramAddrHigh 0x4E
#define PPSMC_MSG_SetDriverDummyTableDramAddrLow 0x4F
-#define PPSMC_Message_Count 0x50
+#define PPSMC_MSG_GetUMCFWWA 0x50
+
+#define PPSMC_Message_Count 0x51
typedef uint32_t PPSMC_Result;
typedef uint32_t PPSMC_Msg;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 061eee1a4c32..e02d036fb298 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -142,6 +142,7 @@ static struct cmn2asic_msg_mapping
navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(SetMGpuFanBoostLimitRpm,
PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
+ MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA,
0),
};
static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
@@ -2278,21 +2279,36 @@ static int
navi10_set_dummy_pstates_table_location(struct smu_context *smu)
static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
{
- uint32_t smu_version;
+ struct amdgpu_device *adev = smu->adev;
+ uint8_t umc_fw_greater_than_v136 = false;
+ uint8_t umc_fw_disable_cdr = false;
+ uint32_t param;
int ret = 0;
- if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
+ if (!navi10_need_umc_cdr_12gbps_workaround(adev))
return 0;
- ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_GET_UMC_FW_WA,
+ 0,
+ ¶m);
if (ret)
return ret;
- /* This workaround is available only for 42.50 or later SMC firmwares */
- if (smu_version < 0x2A3200)
+ /* First bit indicates if the UMC f/w is above v137 */
+ umc_fw_greater_than_v136 = param & 0x1;
+
+ /* Second bit indicates if hybrid-cdr is disabled */
+ umc_fw_disable_cdr = param & 0x2;
+
+ /* w/a only allowed if UMC f/w is <= 136 */
+ if (umc_fw_greater_than_v136)
return 0;
- return navi10_umc_hybrid_cdr_workaround(smu);
+ if (umc_fw_disable_cdr && adev->asic_type == CHIP_NAVI10)
+ return navi10_umc_hybrid_cdr_workaround(smu);
+ else
+ return navi10_set_dummy_pstates_table_location(smu);
}
static void navi10_fill_i2c_req(SwI2cRequest_t *req, bool write,
--
2.28.0
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