AMD General The patch is
Reviewed-by: Hawking Zhang <[email protected]> Regards, Hawking -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Tao Zhou Sent: Wednesday, July 15, 2026 3:48 PM To: [email protected] Cc: Zhou1, Tao <[email protected]> Subject: [PATCH 3/5] drm/amd/ras: add support for old ras eeprom format Handler of some formats will be implemented in the future. Signed-off-by: Tao Zhou <[email protected]> --- drivers/gpu/drm/amd/ras/rascore/ras_umc.h | 17 ++++++++++ .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 31 ++++++++++++++----- 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h index 71b6703193f5..5b9218ebf2ad 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h @@ -46,6 +46,23 @@ #define UMC_ECC_NEW_DETECTED_TAG 0x1 #define UMC_INV_MEM_PFN (0xFFFFFFFFFFFFFFFF) +/* + * a flag to indicate v2 of channel index stored in eeprom + * + * v1 (legacy way): store channel index within a umc instance in eeprom + * range in UMC v12: 0 ~ 7 + * v2: store global channel index in eeprom + * range in UMC v12: 0 ~ 127 + * + * NOTE: it's better to store it in eeprom_table_record.mem_channel, + * but there is only 8 bits in mem_channel, and the channel number may + * increase in the future, we decide to save it in + * eeprom_table_record.retired_page. retired_page is useless in v2, + * we depend on eeprom_table_record.address instead of retired_page in v2. + * Only 48 bits are saved on eeprom, use bit 47 here. + */ +#define UMC_CHANNEL_IDX_V2 BIT_ULL(47) + /* three column bits and one row bit in MCA address flip * in bad page retirement */ diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index 809cbd846883..b8630aba9e64 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -459,16 +459,33 @@ static int convert_eeprom_record_to_nps_addr(struct ras_core_context *ras_core, static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_core, struct eeprom_umc_record *record, uint32_t nps) { - uint64_t pa = 0; + uint64_t ch_idx_v2, pa = 0; + uint32_t save_nps; int ret = 0; - if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) { - record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record); - } else { - ret = convert_eeprom_record_to_nps_addr(ras_core, + save_nps = EEPROM_RECORD_UMC_NPS_MODE(record); + ch_idx_v2 = record->retired_row_pfn & UMC_CHANNEL_IDX_V2; + + if (save_nps || ch_idx_v2) { + if ((nps == save_nps) && !ras_fw_eeprom_supported(ras_core)) { + record->cur_nps_retired_row_pfn = + EEPROM_RECORD_UMC_ADDR_PFN(record); + } else { + ret = convert_eeprom_record_to_nps_addr(ras_core, record, &pa, nps); - if (!ret) - record->cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(pa); + if (!ret) + record->cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(pa); + } + } else { + if (record->address == 0) { + /* for specific old eeprom data, mca address is not stored, + * calc it from pa + */ + } else { + /* old eeprom data format, the scope of channel index is + * limited to umc instance + */ + } } record->cur_nps = nps; -- 2.34.1
