On 12.07.25 00:39, Alex Deucher wrote: > Power control is only available in bare metal. SR-IOV > will need a different method. > > Signed-off-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 3 ++- > 3 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > index 5bbce8544fef0..e6613246d8b8d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > @@ -241,7 +241,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block > *ip_block) > > adev->vcn.supported_reset = > amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); > - adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > + if (!amdgpu_sriov_vf(adev)) > + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > > if (amdgpu_sriov_vf(adev)) { > r = amdgpu_virt_alloc_mm_table(adev); > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > index 6000c528ad6ae..732e9a9293d26 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > @@ -220,7 +220,8 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block > *ip_block) > } > > adev->vcn.supported_reset = > amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); > - adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > + if (!amdgpu_sriov_vf(adev)) > + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > > r = amdgpu_vcn_sysfs_reset_mask_init(adev); > if (r) > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > index 3d3b4254bd729..a137bef918ed5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > @@ -198,7 +198,8 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block > *ip_block) > > adev->vcn.supported_reset = > amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); > - adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > + if (!amdgpu_sriov_vf(adev)) > + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; > > vcn_v5_0_0_alloc_ip_dump(adev); >
