Move the only specific GFX6 part from gfx_v6_0_get_csb_buffer to gfx_get_csb_buffer and remove the gfx6 version.
Signed-off-by: Rodrigo Siqueira <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++++ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 44 +------------------------ 2 files changed, 9 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 57bf3282e797..2c77408b7f0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2254,6 +2254,14 @@ void gfx_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) } } + // GFX6 + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(6, 0, 0) && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(7, 0, 0)) { + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); + } + // GFX7 and GFX8 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(7, 0, 0) && amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index ff794410794d..737ce600c7d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -88,7 +88,6 @@ MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); -static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); static void gfx_v6_0_init_pg(struct amdgpu_device *adev); @@ -2401,7 +2400,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); - gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); + gfx_get_csb_buffer(adev, &dst_ptr[(256/4)]); amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); } @@ -2857,47 +2856,6 @@ static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) -{ - u32 count = 0, i; - const struct cs_section_def *sect = NULL; - const struct cs_extent_def *ext = NULL; - - if (adev->gfx.rlc.cs_data == NULL) - return; - if (buffer == NULL) - return; - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); - buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); - buffer[count++] = cpu_to_le32(0x80000000); - buffer[count++] = cpu_to_le32(0x80000000); - - for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { - for (ext = sect->section; ext->extent != NULL; ++ext) { - if (sect->id == SECT_CONTEXT) { - buffer[count++] = - cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); - buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); - for (i = 0; i < ext->reg_count; i++) - buffer[count++] = cpu_to_le32(ext->extent[i]); - } - } - } - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); - buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); - buffer[count++] = cpu_to_le32(0); -} - static void gfx_v6_0_init_pg(struct amdgpu_device *adev) { if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | -- 2.49.0
