The gfx_v7_0_get_csb_buffer function is incorporated into gfx_get_csb_buffer, but it required to port some specific ASIC operations to the function. Additionally, this transition also eliminates some unnecessary code from gfx_v7_0_get_csb_buffer.
Signed-off-by: Rodrigo Siqueira <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 31 +++++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 68 +------------------------ 2 files changed, 28 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 71a25f626fee..57bf3282e797 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2254,13 +2254,36 @@ void gfx_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) } } - // GFX8 specific operation - if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(8, 0, 0) && + // GFX7 and GFX8 + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(7, 0, 0) && amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0)) { buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); - buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); + + // GFX8 + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(8, 0, 0)) { + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); + } + + // GFX7 Specific ASICs + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(7, 0, 0) && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(8, 0, 0)) { + switch (adev->asic_type) { + case CHIP_BONAIRE: + buffer[count++] = cpu_to_le32(0x16000012); + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_HAWAII: + buffer[count++] = cpu_to_le32(0x3a00161a); + buffer[count++] = cpu_to_le32(0x0000002e); + break; + default: + buffer[count++] = cpu_to_le32(0x00000000); + buffer[count++] = cpu_to_le32(0x00000000); + break; + } + } } // GFX10 and GFX11 specific operation. diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 6423b7a31e84..759d52932842 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -885,7 +885,6 @@ static const u32 kalindi_rlc_save_restore_register_list[] = { }; static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); -static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); static void gfx_v7_0_init_pg(struct amdgpu_device *adev); static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); @@ -3884,70 +3883,6 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) -{ - u32 count = 0, i; - const struct cs_section_def *sect = NULL; - const struct cs_extent_def *ext = NULL; - - if (adev->gfx.rlc.cs_data == NULL) - return; - if (buffer == NULL) - return; - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); - buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); - buffer[count++] = cpu_to_le32(0x80000000); - buffer[count++] = cpu_to_le32(0x80000000); - - for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { - for (ext = sect->section; ext->extent != NULL; ++ext) { - if (sect->id == SECT_CONTEXT) { - buffer[count++] = - cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); - buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); - for (i = 0; i < ext->reg_count; i++) - buffer[count++] = cpu_to_le32(ext->extent[i]); - } - } - } - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); - buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_BONAIRE: - buffer[count++] = cpu_to_le32(0x16000012); - buffer[count++] = cpu_to_le32(0x00000000); - break; - case CHIP_KAVERI: - buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ - buffer[count++] = cpu_to_le32(0x00000000); - break; - case CHIP_KABINI: - case CHIP_MULLINS: - buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ - buffer[count++] = cpu_to_le32(0x00000000); - break; - case CHIP_HAWAII: - buffer[count++] = cpu_to_le32(0x3a00161a); - buffer[count++] = cpu_to_le32(0x0000002e); - break; - default: - buffer[count++] = cpu_to_le32(0x00000000); - buffer[count++] = cpu_to_le32(0x00000000); - break; - } - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); - buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); - - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); - buffer[count++] = cpu_to_le32(0); -} - static void gfx_v7_0_init_pg(struct amdgpu_device *adev) { if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | @@ -4134,7 +4069,6 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { .unset_safe_mode = gfx_v7_0_unset_safe_mode, .init = gfx_v7_0_rlc_init, .get_csb_size = gfx_v7_0_get_csb_size, - .get_csb_buffer = gfx_v7_0_get_csb_buffer, .get_cp_table_num = gfx_v7_0_cp_pg_table_num, .resume = gfx_v7_0_rlc_resume, .stop = gfx_v7_0_rlc_stop, @@ -4482,7 +4416,7 @@ static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block) gfx_v7_0_constants_init(adev); /* init CSB */ - adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); + gfx_get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); /* init rlc */ r = adev->gfx.rlc.funcs->resume(adev); if (r) -- 2.49.0
