Am 12.07.2017 um 22:31 schrieb Felix Kuehling:
I'm wondering if you need a HDP flush in update_directories at all. Are
there cases where the directories are updated but the page tables are not?
It can happen that a page table is swapped out and back in. In this case
on the PDs need an update, but not the table itself.
Rather unlikely, but still possible.
Also, in case of amdgpu_cs, I think we already have an HPD flush anyway.
For KFD we don't use kernel-based submission, so we'd have to add an HDP
flush into the KFD-specific VM mapping code.
Yeah, good point. But during CS the HDP flush comes after the VM flush.
I think we could change that, but I'm not 100% sure what the
interactions with SRVIO are.
Christian.
Either way, this is Reviewed-by: Felix Kuehling <[email protected]>
Regards,
Felix
On 17-07-12 04:31 AM, Christian König wrote:
From: Christian König <[email protected]>
No need to do this after every single update.
Signed-off-by: Christian König <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f52a358..1c6018b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -991,10 +991,6 @@ static void amdgpu_vm_cpu_set_ptes(struct
amdgpu_pte_update_params *params,
i, value, flags);
addr += incr;
}
-
- /* Flush HDP */
- mb();
- amdgpu_gart_flush_gpu_tlb(params->adev, 0);
}
static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1237,6 +1233,12 @@ int amdgpu_vm_update_directories(struct amdgpu_device
*adev,
if (r)
amdgpu_vm_invalidate_level(&vm->root);
+ if (vm->use_cpu_for_update) {
+ /* Flush HDP */
+ mb();
+ amdgpu_gart_flush_gpu_tlb(adev, 0);
+ }
+
return r;
}
@@ -1745,6 +1747,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_add(&bo_va->vm_status, &vm->cleared);
spin_unlock(&vm->status_lock);
+ if (vm->use_cpu_for_update) {
+ /* Flush HDP */
+ mb();
+ amdgpu_gart_flush_gpu_tlb(adev, 0);
+ }
+
return 0;
}
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