From 8f8a8b6e519c2b7d882df720852ab9e09554c1f3 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Thu, 13 Aug 2009 11:51:52 -0400 Subject: [PATCH] Use proper membar/stbar instructions on SPARC Cc: David S. Miller Cc: Alan Coopersmith Signed-off-by: Matt Turner --- hw/xfree86/common/compiler.h | 35 ++++++++++++++++++++++++----------- 1 files changed, 24 insertions(+), 11 deletions(-) diff --git a/hw/xfree86/common/compiler.h b/hw/xfree86/common/compiler.h index 31d97b1..57087e6 100644 --- a/hw/xfree86/common/compiler.h +++ b/hw/xfree86/common/compiler.h @@ -195,9 +195,22 @@ extern unsigned short ldw_brx(volatile unsigned char *, int); # elif defined __sparc__ -# define barrier() __asm__ __volatile__ (".word 0x8143e00a" : : : "memory") -# define mem_barrier() /* XXX: nop for now */ -# define write_mem_barrier() /* XXX: nop for now */ +# if defined __sparc_v9__ +# define mem_barrier() \ + __asm__ __volatile__ ("ba,pt %%xcc, 1f\n\t" \ + "membar #Lookaside\n" \ + "1:\n" \ + : : : "memory") +# define write_mem_barrier() \ + __asm__ __volatile__ ("ba,pt %%xcc, 1f\n\t" \ + "membar #StoreStore\n" \ + "1:\n" \ + : : : "memory") +# else /* !__arch64__ */ +# define write_mem_barrier() __asm__ __volatile__ ("stbar" : : : "memory") +# define mem_barrier() write_mem_barrier() +# endif /* __arch64__ */ + # endif # endif /* __GNUC__ */ # endif /* NO_INLINE */ @@ -494,7 +507,7 @@ outb(unsigned long port, unsigned char val) __asm__ __volatile__("stba %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (port), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -503,7 +516,7 @@ outw(unsigned long port, unsigned short val) __asm__ __volatile__("stha %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (port), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -512,7 +525,7 @@ outl(unsigned long port, unsigned int val) __asm__ __volatile__("sta %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (port), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ unsigned int @@ -614,7 +627,7 @@ xf86WriteMmio8(__volatile__ void *base, const unsigned long offset, __asm__ __volatile__("stba %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (addr), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -626,7 +639,7 @@ xf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset, __asm__ __volatile__("sth %0, [%1]" : /* No outputs */ : "r" (val), "r" (addr)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -638,7 +651,7 @@ xf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset, __asm__ __volatile__("stha %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (addr), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -650,7 +663,7 @@ xf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset, __asm__ __volatile__("st %0, [%1]" : /* No outputs */ : "r" (val), "r" (addr)); - barrier(); + write_mem_barrier(); } static __inline__ void @@ -662,7 +675,7 @@ xf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset, __asm__ __volatile__("sta %0, [%1] %2" : /* No outputs */ : "r" (val), "r" (addr), "i" (ASI_PL)); - barrier(); + write_mem_barrier(); } static __inline__ void -- 1.6.3.3