On Fri, 11 Jun 2021, Jan Beulich wrote:
> The Arm ARM's description of MSR (ARM DDI 0406C.d section B9.3.12)
> doesn't even allow for plain "SPSR" here, and while gas accepts this, it
> takes it to mean SPSR_cf. Yet surely all of SPSR wants updating on this
> path, not just the lowest and highest 8 bits.
>
> Fixes: dfcffb128be4 ("xen/arm32: SPSR_hyp/SPSR")
> Signed-off-by: Jan Beulich <[email protected]>
Thanks for the patch! I disassembled the instruction in the bad Xen
binary and confirmed that 2 of the mask bits are off.
Rebuilding the binary with your patch applied solves the issue: now are
4 bits are set.
Thank you so much!
Reviewed-by: Stefano Stabellini <[email protected]>
> ---
> v2: Add doc ref.
>
> --- a/xen/arch/arm/arm32/entry.S
> +++ b/xen/arch/arm/arm32/entry.S
> @@ -395,7 +395,7 @@ return_to_hypervisor:
> ldr r11, [sp, #UREGS_pc]
> msr ELR_hyp, r11
> ldr r11, [sp, #UREGS_cpsr]
> - msr SPSR, r11
> + msr SPSR_cxsf, r11
> #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR
> /*
> * Hardening branch predictor may require to setup a different
>
