Hello Oleksandr, > On 30 Oct 2020, at 10:44 am, Oleksandr Andrushchenko > <[email protected]> wrote: > > Hi, Rahul! > > On 10/20/20 6:25 PM, Rahul Singh wrote: >> Add support for ARM architected SMMUv3 implementations. It is based on >> the Linux SMMUv3 driver. >> >> Major differences between the Linux driver are as follows: >> 1. Only Stage-2 translation is supported as compared to the Linux driver >> that supports both Stage-1 and Stage-2 translations. > > First of all thank you for the efforts! > > I tried the patch with QEMU and would like to know if my understanding correct > > that this combination will not work as of now: > > (XEN) SMMUv3: /smmuv3@9050000: SMMUv3: DT value = eventq
I have limited knowledge about QEMU internals.As what I see from the logs, fault is occurred at early driver initialisation when SMMU driver is trying to probe the HW. > (XEN) Data Abort Trap. Syndrome=0x1940010 > (XEN) Walking Hypervisor VA 0x40031000 on CPU0 via TTBR 0x00000000b8469000 > (XEN) 0TH[0x0] = 0x00000000b8468f7f > > [snip] > > If this is expected then is there any plan to make QEMU work as well? > > I see [1] says that "Only stage 1 and AArch64 PTW are supported." on QEMU > side. Yes as of now only Stage-2 is supported in XEN.If we have any requirement or use case that depends on Stage-1 translation we can support that also in XEN. > > > We are interested in QEMU/SMMUv3 as a flexible platform for PCI passthrough > > implementation, so it could allow testing different setups and configurations > with QEMU. > > > Thank you in advance, > > Oleksandr > > [1] > https://patchwork.ozlabs.org/project/qemu-devel/cover/[email protected]/ Regards, Rahul
