>>> On 26.04.19 at 12:22, <[email protected]> wrote: > Currently, configuration of the SYSENTER MSRs are behind a vendor check for > Intel and Centaur, but this misses Zhaoxin. > > Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early > for AMD processors, which can't use SYSENTER/SYSEXIT when operating in long > mode. > > Suggested-by: Jan Beulich <[email protected]> > Signed-off-by: Andrew Cooper <[email protected]>
Reviewed-by: Jan Beulich <[email protected]> _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
