On Thu, Oct 25, 2018 at 03:22:17AM -0600, Jan Beulich wrote: > >>> On 15.10.18 at 13:19, <[email protected]> wrote: > > On Fri, Oct 12, 2018 at 08:14:36AM -0600, Jan Beulich wrote: > >> >>> On 04.10.18 at 17:43, <[email protected]> wrote: > >> > It is used by PV code only. > >> > >> And wrongly so - the same is needed for a PVH Dom0 afaict. > > > > Yes, looking at the models affected by this issue according to > > init_amd it seems to cover the full AMD line (from family 0xf to > > 0x17). I don't seem to find a reference in the code to the Errata, do > > you know if there's some formal description of it? > > I don't recall this having been considered an erratum. > > Checking just the Fam10 and Fam15 BKDGs, I'm getting the > impression that Fam15 does not have the issue worked around > here. It might further be that not even all Fam10 steppings are > affected. Brian - any chance you could clarify this for us? > > Independent of the range of systems affected I still think that > PVH Dom0 behavior here ought to be the same as PV Dom0's. > > Jan >
Just an FYI, I'm looking into it. I might require to an email to an engineer who's always extremely busy, so it might take a little while. -- Brian Woods _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
