On 04.03.2026 20:53, Kevin Lampis wrote:
> struct cpuinfo_x86
> .x86 => .family
> .x86_vendor => .vendor
> .x86_model => .model
> .x86_mask => .stepping
>
> No functional change.
>
> This work is part of making Xen safe for Intel family 18/19.
>
> Signed-off-by: Kevin Lampis <[email protected]>
> ---
> I couldn't find any information about these Intel family 6 processors:
> model 0x5d: /* SoFIA 3G Granite/ES2.1 */
> model 0x65: /* SoFIA LTE AOSP */
> model 0x6e: /* Cougar Mountain */
> Should I add them to intel-family.h?
We should keep that in sync with Linux, I think, so "no" unless you mean to
first have respective entries added there.
0x5d is listed in the SDM, so I'd recommend keeping the entries (using IFM()
directly for the time being).
0x65 and 0x6e aren't listed in the SDM, so may never really have hit the
public. Respective cases can perhaps be dropped, but such dropping would
again likely better be done in a separate change.
> @@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void)
> * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
> * this time.
> */
> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return false;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> /*
> * Core processors since at least Nehalem are vulnerable.
> */
> - case 0x1f: /* Auburndale / Havendale */
> - case 0x1e: /* Nehalem */
> - case 0x1a: /* Nehalem EP */
> - case 0x2e: /* Nehalem EX */
> - case 0x25: /* Westmere */
> - case 0x2c: /* Westmere EP */
> - case 0x2f: /* Westmere EX */
> - case 0x2a: /* SandyBridge */
> - case 0x2d: /* SandyBridge EP/EX */
> - case 0x3a: /* IvyBridge */
> - case 0x3e: /* IvyBridge EP/EX */
> - case 0x3c: /* Haswell */
> - case 0x3f: /* Haswell EX/EP */
> - case 0x45: /* Haswell D */
> - case 0x46: /* Haswell H */
> - case 0x3d: /* Broadwell */
> - case 0x47: /* Broadwell H */
> - case 0x4f: /* Broadwell EP/EX */
> - case 0x56: /* Broadwell D */
> - case 0x4e: /* Skylake M */
> - case 0x5e: /* Skylake D */
> - case 0x55: /* Skylake-X / Cascade Lake */
> - case 0x7d: /* Ice Lake */
> - case 0x7e: /* Ice Lake */
> - case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
> - case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
> - case 0xa5: /* Comet Lake H/S */
> - case 0xa6: /* Comet Lake U */
> + case INTEL_NEHALEM_G:
> + case INTEL_NEHALEM:
> + case INTEL_NEHALEM_EP:
> + case INTEL_NEHALEM_EX:
> + case INTEL_WESTMERE:
> + case INTEL_WESTMERE_EP:
> + case INTEL_WESTMERE_EX:
> + case INTEL_SANDYBRIDGE:
> + case INTEL_SANDYBRIDGE_X:
> + case INTEL_IVYBRIDGE:
> + case INTEL_IVYBRIDGE_X:
> + case INTEL_HASWELL:
> + case INTEL_HASWELL_X:
> + case INTEL_HASWELL_L:
> + case INTEL_HASWELL_G:
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> + case INTEL_SKYLAKE_L:
> + case INTEL_SKYLAKE:
> + case INTEL_SKYLAKE_X:
> + case INTEL_ICELAKE:
> + case INTEL_ICELAKE_L:
> + case INTEL_KABYLAKE_L:
> + case INTEL_KABYLAKE:
> + case INTEL_COMETLAKE:
> + case INTEL_COMETLAKE_L:
> return true;
>
> /*
> * Atom processors are not vulnerable.
> */
> - case 0x1c: /* Pineview */
> - case 0x26: /* Lincroft */
> - case 0x27: /* Penwell */
> - case 0x35: /* Cloverview */
> - case 0x36: /* Cedarview */
> - case 0x37: /* Baytrail / Valleyview (Silvermont) */
> - case 0x4d: /* Avaton / Rangely (Silvermont) */
> - case 0x4c: /* Cherrytrail / Brasswell */
> - case 0x4a: /* Merrifield */
> - case 0x5a: /* Moorefield */
> - case 0x5c: /* Goldmont */
> - case 0x5d: /* SoFIA 3G Granite/ES2.1 */
> - case 0x65: /* SoFIA LTE AOSP */
> - case 0x5f: /* Denverton */
> - case 0x6e: /* Cougar Mountain */
> - case 0x75: /* Lightning Mountain */
> - case 0x7a: /* Gemini Lake */
> - case 0x86: /* Jacobsville */
> + case INTEL_ATOM_BONNELL:
> + case INTEL_ATOM_BONNELL_MID:
> + case INTEL_ATOM_SALTWELL_MID:
> + case INTEL_ATOM_SALTWELL_TABLET:
> + case INTEL_ATOM_SALTWELL:
> + case INTEL_ATOM_SILVERMONT:
> + case INTEL_ATOM_SILVERMONT_D:
> + case INTEL_ATOM_AIRMONT:
> + case INTEL_ATOM_SILVERMONT_MID:
> + case INTEL_ATOM_SILVERMONT_MID2:
Can the Silvermonts please be grouped together?
> + case INTEL_ATOM_GOLDMONT:
> + //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ???
> + //case 0x65: /* SoFIA LTE AOSP */ // XXX ???
> + case INTEL_ATOM_GOLDMONT_D:
> + //case 0x6e: /* Cougar Mountain */ // XXX ???
> + case INTEL_ATOM_AIRMONT_NP:
Same for the Airmonts and ...
> + case INTEL_ATOM_GOLDMONT_PLUS:
... the Goldmonts.
> @@ -3431,23 +3435,20 @@ static void __init lbr_tsx_fixup_check(void)
> * fixed up as well.
> */
> if ( cpu_has_hle || cpu_has_rtm ||
> - boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> - case 0x3c: /* HSM182, HSD172 - 4th gen Core */
> - case 0x3f: /* HSE117 - Xeon E5 v3 */
> - case 0x45: /* HSM182 - 4th gen Core */
> - case 0x46: /* HSM182, HSD172 - 4th gen Core (GT3) */
> - case 0x3d: /* BDM127 - 5th gen Core */
> - case 0x47: /* BDD117 - 5th gen Core (GT3)
> - BDW117 - Xeon E3-1200 v4 */
> - case 0x4f: /* BDF85 - Xeon E5-2600 v4
> - BDH75 - Core-i7 for LGA2011-v3 Socket
> - BDX88 - Xeon E7-x800 v4 */
> - case 0x56: /* BDE105 - Xeon D-1500 */
> + case INTEL_HASWELL:
> + case INTEL_HASWELL_X:
> + case INTEL_HASWELL_L:
> + case INTEL_HASWELL_G:
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> break;
I think it would be nice for the errata numbers to not be lost.
> @@ -3476,19 +3477,16 @@ static void __init ler_to_fixup_check(void)
> * that are not equal to bit[47]. Attempting to context switch this
> value
> * may cause a #GP. Software should sign extend the MSR.
> */
> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> - case 0x3d: /* BDM131 - 5th gen Core */
> - case 0x47: /* BDD??? - 5th gen Core (H-Processor line)
> - BDW120 - Xeon E3-1200 v4 */
> - case 0x4f: /* BDF93 - Xeon E5-2600 v4
> - BDH80 - Core-i7 for LGA2011-v3 Socket
> - BDX93 - Xeon E7-x800 v4 */
> - case 0x56: /* BDE??? - Xeon D-1500 */
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> ler_to_fixup_needed = true;
> break;
> }
Same here then.
Jan
