On 3/4/26 3:54 PM, Oleksii Kurochko wrote:
+ if ( riscv_isa_extension_available(NULL,
RISCV_ISA_EXT_smstateen) )
+ {
+ INIT_CSR_MASK(HSTATEEN0, hstateen0, _UL(0xDE00000000000007));
+ csr_masks.ro_one.hstateen0 = old;
What guarantees that only r/o-one bits are set in the incoming
hstateen0? I
can't help thinking that to determine those bits you want to use
csr_read_clear() (or csr_clear()).
Good point, then after INIT_CSR_MASK() it will be needed to do:
csr_masks.ro_one.hstateen0 = csr_read_clear(CSR_HSTATEEN0,
_UL(0xDE00000000000007));
csr_swap(CSR_HSTATEEN0, old);
Probably, csr_swap() isn't needed as it would be good to have all
writable bits by
default 0. Of course, except r/o-one bits.
I came up with the macros declared inside init_csr_masks():
#define INIT_RO_ONE_MASK(csr, field, mask) do { \
old = csr_read_clear(CSR_HSTATEEN0, mask); \
csr_masks.ro_one.field = csr_swap(CSR_##csr, old) & mask; \
} while (0)
~ Oleksii
