On 20.02.2026 16:53, Teddy Astie wrote:
> Temperature sensors MSR were previously assumed to be available when "DTS"
> CPUID bit is set. This is not really the case :
> * MSR_IA32_THERM_STATUS is gated behind ACPI CPUID bit, only DTS-related bits
> of this MSR are gated behind the DTS CPUID
> * MSR_PACKAGE_THERM_STATUS is gated behind "PTM" CPUID
>
> Also adjust the MSR_TEMPERATURE_TARGET which is not architectural, but stable
> in practice, and required to be exposed for reliably querying CPU temperature.
>
> Fixes: 615c9f3f820 ("x86/platform: Expose DTS sensors MSR")
> Reported-by: Tu Dinh <[email protected]>
> Signed-off-by: Teddy Astie <[email protected]>
Reviewed-by: Jan Beulich <[email protected]>
> --- a/xen/arch/x86/platform_hypercall.c
> +++ b/xen/arch/x86/platform_hypercall.c
> @@ -89,9 +89,26 @@ static bool msr_read_allowed(unsigned int msr)
> return cpu_has_srbds_ctrl;
>
> case MSR_IA32_THERM_STATUS:
> + return host_cpu_policy.basic.acpi;
> +
> + /*
> + * This MSR is present on most Intel Core-family CPUs since Nehalem but
> is not an
> + * architectural MSR. No CPUID bit enumerates this MSR.
> + *
> + * This MSR exposes "temperature target" that is needed to compute the
> CPU
> + * temperature. The "temperature target" is a model specific value, and
> this MSR is
> + * the only known method of getting the one used for the CPU. On some
> CPU models with
> + * Intel SST-PP, the "temperature target" can vary over time.
> + *
> + * We assume all Intel CPUs with DTS may support this MSR; but reads can
> fail in case
> + * the platform doesn't actually support this MSR.
> + */
> case MSR_TEMPERATURE_TARGET:
> + return boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> + host_cpu_policy.basic.digital_temp_sensor;
Personally I think indentation wants to be three deeper here, but this is one
of the grey areas of our style. I may take the liberty to adjust it while
committing.
Jan
