On Fri, Feb 20, 2026 at 10:42:57AM +0000, Andrew Cooper wrote: > From: Sohil Mehta <[email protected]> > > X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag. > It is used across several vendors. Intel CPUs will set the feature when > the architectural CPUID.80000007.EDX[1] bit is set. There are also some > Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't > enumerate it with the architectural bit. Those currently have a model > range check. > > Today, virtually all of the CPUs that have the CPUID bit *also* match > the "model >= 0x0e" check. This is confusing. Instead of an open-ended > check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end > of goofy CPUs that should enumerate the bit but don't. These models are > relatively arbitrary but conservative pick for this. > > This makes it obvious that later CPUs (like Family 18+) no longer need > to synthesize X86_FEATURE_CONSTANT_TSC. > > Signed-off-by: Sohil Mehta <[email protected]> > Signed-off-by: Ingo Molnar <[email protected]> > Link: https://lore.kernel.org/r/[email protected] > Link: https://git.kernel.org/tip/fadb6f569b10bf668677add876ed50586931b8f3 > [Port to Xen] > Signed-off-by: Kevin Lampis <[email protected]> > Signed-off-by: Andrew Cooper <[email protected]>
Acked-by: Roger Pau Monné <[email protected]> Thanks, Roger.
