* Xin Li (Intel) <[email protected]> wrote:
> - __wrmsr (MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32);
> + native_wrmsrl(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3);
This is an improvement.
> - __wrmsr (MSR_IA32_PQR_ASSOC, rmid_p, plr->closid);
> + native_wrmsrl(MSR_IA32_PQR_ASSOC, (u64)plr->closid << 32 | rmid_p);
> - __wrmsr (MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
> + native_wrmsrl(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p);
This is not an improvement.
Please provide a native_wrmsrl() API variant where natural [rmid_p, closid_p]
high/lo parameters can be used, without the shift-uglification...
Thanks,
Ingo