On 28.02.2025 17:24, Andrew Cooper wrote:
> On 27/02/2025 8:11 am, Jan Beulich wrote:
>> On 26.02.2025 18:20, Andrew Cooper wrote:
>>> --- a/xen/arch/riscv/include/asm/bitops.h
>>> +++ b/xen/arch/riscv/include/asm/bitops.h
>>> @@ -125,6 +125,13 @@ static inline void clear_bit(int nr, volatile void *p)
>>> #undef NOT
>>> #undef __AMO
>>>
>>> +#define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0)
>>> +#define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0)
>>> +#define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0)
>> I fear you won't like me to say this, but can't we avoid baking in yet
>> another assumption on sizeof(int) == 4, by using at least sizeof(int) * 8
>> here (yet better might be sizeof(int) * BITS_PER_BYTE)?
>
> Yes and no.
>
> No, because 32 here is consistent with ARM and PPC when it comes to
> arch_fls(). Given the effort it took to get these consistent, I'm not
> interested in letting them diverge.
>
> But, if someone wants to introduce BITS_PER_INT to mirror BITS_PER_LONG
> and use it consistently, then that would be ok too.
I was actually hoping to eliminate BITS_PER_LONG at some point, in favor
of using sizeof(long) * BITS_PER_BYTE. (Surely in common code we could
retain a shorthand of that name, if so desired, but I see no reason why
each arch would need to provide all three BITS_PER_{BYTE,INT,LONG}.)
Jan
