On 24/07/2024 8:56 am, Jan Beulich wrote: > On 23.07.2024 22:37, Andrew Cooper wrote: >> XenServer's instance of coverity complains of OVERFLOW_BEFORE_WIDEN in >> mask_and_ack_level_ioapic_irq(), which is ultimately because of v being >> unsigned long, and (1U << ...) being 32 bits. > Which of course is bogus when the shift amount is masked down to 5 bits. > May I ask that you express this somehow in the wording.
How about this? Coverity's reasoning isn't correct. (1U << (x & 0x1f)) can't ever overflow, but the complaint is really based on having to expand the RHS. While this can be fixed by changing v to be unsigned int, take the opportunity to better still. > >> Introduce a apic_tmr_read() helper like we already have for ISR and IRR, and >> use it to remove the opencoded access logic. Introduce an is_level boolean >> to >> improve the legibility of the surrounding logic. >> >> No functional change. >> >> Signed-off-by: Andrew Cooper <[email protected]> > The change is an improvement irrespective of Coverity's anomaly, so: > Reviewed-by: Jan Beulich <[email protected]> Thanks.
