On 02.07.2024 13:01, Oleksii Kurochko wrote:
> RISC-V does a conditional toolchain for the Zbb extension
> (xen/arch/riscv/rules.mk), but unconditionally uses the
> ANDN instruction in emulate_xchg_1_2().
>
> Fixes: 51dabd6312c ("xen/riscv: introduce cmpxchg.h")
>
> Suggested-by: Andrew Cooper <[email protected]>
> Signed-off-by: Oleksii Kurochko <[email protected]>
> Suggested-By: Jan Beulich <[email protected]>
Hmm, meant to say that for the earlier patch already: A Suggested-by:
after an S-o-b is somewhat odd. You can't have signed off a change
before it was suggested, as you can't possibly have written it then.
Otoh I'm not sure tagging me is appropriate here anyway.
> --- a/xen/arch/riscv/include/asm/cmpxchg.h
> +++ b/xen/arch/riscv/include/asm/cmpxchg.h
> @@ -18,6 +18,19 @@
> : "r" (new) \
> : "memory" );
>
> +/*
> + * To not face an issue that gas doesn't understand ANDN instruction
> + * it is encoded using .insn directive.
> + */
> +#ifdef __riscv_zbb
> +#define ANDN_INSN(rd, rs1, rs2) \
> + ".insn r 0x33, 0x7, 0x20, " rd ", " rs1 ", " rs2 "\n"
Why 0x33? Just like in the other patch you used MISC_MEM (as suggested,
for being more descriptive), you want to use OP here. Then
Reviewed-by: Jan Beulich <[email protected]>
(and I'd certainly be okay making the change while committing)
Jan
