This run is configured for baseline tests only. flight 74855 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/74855/
Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf a05a8a5aa17da4bc7144706a9931d68beec1a61f baseline version: ovmf eb5943134630292db2c14346b5d94eab0b72314f Last test of basis 74839 2018-06-10 07:54:36 Z 1 days Testing same since 74855 2018-06-11 16:23:52 Z 0 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Leo Duran <[email protected]> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass ------------------------------------------------------------ sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ------------------------------------------------------------ commit a05a8a5aa17da4bc7144706a9931d68beec1a61f Author: Leo Duran <[email protected]> Date: Fri May 25 03:07:30 2018 +0800 MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Put the UART in FIFO Polled Mode by clearing IER after setting FCR. Also, add comments to show DLAB state for registers 0 and 1. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <[email protected]> Cc: Star Zeng <[email protected]> CC: Eric Dong <[email protected]> Reviewed-by: Ruiyu Ni <[email protected]> Reviewed-by: Star Zeng <[email protected]> _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
