On 12.01.2024 12:09, Roger Pau Monne wrote: > When Architectural Performance Monitoring is available, the PERF_GLOBAL_CTRL > MSR contains per-counter enable bits that is ANDed with the enable bit in the > counter EVNTSEL MSR in order for a PMC counter to be enabled. > > So far the watchdog code seems to have relied on the PERF_GLOBAL_CTRL enable > bits being set by default, but at least on some Intel Sapphire and Emerald > Rapids this is no longer the case, and Xen reports: > > Testing NMI watchdog on all CPUs: 0 40 stuck > > The first CPU on each package is started with PERF_GLOBAL_CTRL zeroed, so PMC0 > doesn't start counting when the enable bit in EVNTSEL0 is set, due to the > relevant enable bit in PERF_GLOBAL_CTRL not being set. > > Check and adjust PERF_GLOBAL_CTRL during CPU initialization so that all the > general-purpose PMCs are enabled. Doing so brings the state of the > package-BSP > PERF_GLOBAL_CTRL in line with the rest of the CPUs on the system. > > Signed-off-by: Roger Pau Monné <[email protected]>
Acked-by: Jan Beulich <[email protected]>
