On 22.11.2023 13:25, Andrew Cooper wrote: > On 22/11/2023 7:43 am, Jan Beulich wrote: >> --- a/xen/tools/gen-cpuid.py >> +++ b/xen/tools/gen-cpuid.py >> @@ -274,7 +274,7 @@ def crunch_numbers(state): >> # superpages, PCID and PKU are only available in 4 level paging. >> # NO_LMSL indicates the absense of Long Mode Segment Limits, which >> # have been dropped in hardware. >> - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL], >> + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI], > > I know this is what the ISE says, but I'm not sure it's a legitimate > dependency. > > It is an implementation detail that Intel depend on a RIP-relative > address, but there are no architectural reason why other implementations > couldn't make this work in 32bit too. > > The worst that happens without this dependency is that 32bit-only VMs > see a hint bit about certain NOPs having uarch side effects, which > they'll ignore for other reasons.
I'm okay either way. Adding the dependency was the only reason to have a v2 ... > So I recommend dropping the dependency. If you're happy, then > Reviewed-by: Andrew Cooper <[email protected]> Thanks. Jan
