This is a micro-optimsiation for Silvermont microarchitectures, which don't recognise the 64bit form as a zeroing idiom.
No functional change. Signed-off-by: Andrew Cooper <[email protected]> --- CC: Jan Beulich <[email protected]> CC: Roger Pau Monné <[email protected]> CC: Wei Liu <[email protected]> --- xen/arch/x86/x86_64/entry.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index b53d862089d7..cb794167c127 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -1027,7 +1027,7 @@ handle_ist_exception: * Interrupted guest context. Clear the restore value for xen_cr3 * and copy the context to stack bottom. */ - xor %r15, %r15 + xor %r15d, %r15d xor %ebx, %ebx GET_CPUINFO_FIELD(guest_cpu_user_regs,di) movq %rsp,%rsi base-commit: fa2da5bce90b3777aa7a323e1cf201c97b56d278 prerequisite-patch-id: a9e4e1e34d08e876d1fcb3299c6d563086768722 prerequisite-patch-id: 703590f2c99382f6509c94bb5955f47ab2d7c57d -- 2.30.2
