On Thu, May 11, 2023 at 02:07:40PM +0200, Jan Beulich wrote: > This controls the driving of IGNNE# (if such emulation is enabled in > hardware), and hence would need proper handling in the hypervisor to be > safe to use by Dom0 (and fully emulating for PVH/HVM DomU-s). > > Signed-off-by: Jan Beulich <[email protected]>
Acked-by: Roger Pau Monné <[email protected]> > --- > RFC: Really this disabling of access would want to be conditional upon > the functionality actually being enabled. For AMD this looks to be > uniformly HWCR[8], but for Intel this is chipset-specific. I'm afraid I'm not able to find much information about this, I've found something in the Intel PCH datasheets, but I don't have a clear picture of whether this port could be used by other functionality. >From my reading of the spec, the initial value in 0xF0 (COPROC_ERR) will inhibit the generation of an IRQ13, and hence if the behavior that most modern OSes rely on? Mostly wanted to check which kind of logic and OS would use to figure out whether 0xF0 exists and control IGNNE# Thanks, Roger.
