On 18/04/2023 12:26, Oleg Nikitenko wrote:
Hi Julien,
Hi Oleg,
This feature has not been merged in Xen upstream yet
would assume that upstream + the series on the ML [1] work
Please clarify this point.
Because the two thoughts are controversial.
It is not clear to me how what I wrote is controversial. A series was
sent on the ML for cache coloring support and this was tested on Xilinx
ZynqMP (see cover letter).
This work was sponsored by Xilinx/AMD. So my assumption is they have
done the same amount of testing as they did for their own branch.
Cheers,
--
Julien Grall
