Hi Ayan,
On 30/10/2022 00:48, Ayan Kumar Halder wrote:
>
>
> Refer ARM DDI 0487G.b ID072021, B2.2.1
Please refer to the latest spec.
Apart from that...
> "Requirements for single-copy atomicity
>
> - A read that is generated by a load instruction that loads a single
> general-purpose register and is aligned to the size of the read in the
> instruction is single-copy atomic.
>
> -A write that is generated by a store instruction that stores a single
> general-purpose register and is aligned to the size of the write in the
> instruction is single-copy atomic"
>
> On AArch32, the alignment check is enabled at boot time by setting HSCTLR.A
> bit.
> ("HSCTLR, Hyp System Control Register").
> However in AArch64, alignment check is not enabled at boot time.
>
> Thus, one needs to check for alignment when performing atomic operations.
>
> Signed-off-by: Ayan Kumar Halder <[email protected]>
Reviewed-by: Michal Orzel <[email protected]
~Michal
