On 26.08.2022 14:50, Carlo Nonato wrote: > Shared caches in multi-core CPU architectures represent a problem for > predictability of memory access latency. This jeopardizes applicability > of many Arm platform in real-time critical and mixed-criticality > scenarios. We introduce support for cache partitioning with page > coloring, a transparent software technique that enables isolation > between domains and Xen, and thus avoids cache interference. > > When creating a domain, a simple syntax (e.g. `0-3` or `4-11`) allows > the user to define assignments of cache partitions ids, called colors, > where assigning different colors guarantees no mutual eviction on cache > will ever happen. This instructs the Xen memory allocator to provide > the i-th color assignee only with pages that maps to color i, i.e. that > are indexed in the i-th cache partition. > > The proposed implementation supports the dom0less feature. > The solution has been tested in several scenarios, including Xilinx Zynq > MPSoCs.
Having looked at the non-Arm-specific parts of this I have one basic question: Wouldn't it be possible to avoid the addition of entirely new logic by treating the current model as just using a single color, therefore merely becoming a special case of what you want? Plus an advanced question: In how far does this interoperate with static allocation, which again is (for now) an Arm-only feature? Your reference to dom0less above doesn't cover this afaict. Jan
