On 24.11.2021 02:22, Tian, Kevin wrote: >> From: Jan Beulich <[email protected]> >> Sent: Tuesday, November 23, 2021 9:40 PM >> >> Bit 0 of the capability register field has become reserved at or before > > Bit 0 of 'SAGAW' in the capability register ...
I've changed it, but I thought the use of "field" in the sentence together with the title would be entirely unambiguous. >> spec version 2.2. Treat it as such. Replace the effective open-coding of >> find_first_set_bit(). Adjust local variable types. >> >> Signed-off-by: Jan Beulich <[email protected]> >> --- >> Strictly speaking IOMMUs supporting only 3-level tables ought to result >> in guests seeing a suitably reduced physical address width in CPUID. >> And then the same would apply to restrictions resulting from MGAW. > > Yes. I remember there was some old discussion in Qemu community > for whether guest physical addr width should be based on IOMMU > constraints when passthrough device is used. But it didn't go anywhere > (and I cannot find the link...) I've added an item to my todo list. > anyway with above comment fixed: > > Reviewed-by: Kevin Tian <[email protected]> Thanks. Jan
