OpenOCD should work, although you'll have to do some legwork on your own to make it happen. It has JTAG adapter configurations built-in for the HS3 family, as well as some of the Zynq-7000 family. It doesn't have board files for the COTS dev boards, though.
My workflow to bring up a board from scratch was: - Configure and build a minimal bitstream and FSBL using XIlinx Vivado and SDK, respectively. - Boot the target to JTAG mode. Read the Zynq-7000 TRM section on the boot process to see how the boot mode select pins work with the ROM Bootloader's flow, as well as your board's schematic. - Load the FSBL into OCM and run it. In the default configuration, it should remain in JTAG mode. At this point, ps7_init (PS I/O pin configuration) and DDR init should be done. It is possible to perform I/O initialization directly from OpenOCD and Vivado's TCL, but we didn't bother with that workflow. - Load programs into DDR and run those. For your workflow, it may be the initial load of u-boot which you use to initialize your flash memories. You could also load an RTEMS program directly to DDR instead. See also https://devel.rtems.org/wiki/Debugging/OpenOCD/Xilinx_Zynq I didn't follow his process exactly, but found it quite informative. Upstream OpenOCD provides an adequate Zynq-7000 target file nowadays. An example board file for the microzed with an HS3 JTAG: ``` source [find interface/ftdi/digilent_jtag_hs3.cfg] transport select jtag reset_config srst_only srst_push_pull source [find target/zynq_7000.cfg] # The adapter needs to be extra slow until PS clocks are all the way up. Can raise to 20 MHz after running the FSBL adapter_khz 2000 ``` I'm using the same target/zynq_7000.cfg supplied with OpenOCD, except that I add the following utility function: ``` proc zynqpl_reset_release {target} { # Unlock SLCR $target mww 0xf8000008 0xdf0d # Enable level shifters, both PL-PS and PS-PL $target mww 0xf8000900 0xF # Release FPGA reset $target mww 0xf8000240 0x0 # Lock SLCR $target mww 0xf8000004 0x767b } ``` A script to load an execute everything from the reset condition on the microzed looks like this. Obviously those paths are to artifacts of our specific build system, but hopefully this can serve as a jumping-off point for you. ``` # Load the FSBL into OCM and run it. init halt targets zynq.cpu0 load_image arm-none-eabi/bin/microzed_usrp_fsbl.elf 0x000 elf resume 0 sleep 2000 halt adapter_khz 20000 # FPGA fabric sequence. zynqpl_program zynq_pl.bs pld load 0 fsbl/microzed_usrp_platform/microzed_top.bit sleep 100 zynqpl_reset_release zynq.cpu0 # At this point, MIO, EMIO, and DDR are all set up. Load the application program into # DDR. load_image arm-rtems5/bin/microzed-rtems.elf # Force ARM core state in case the halt was in Thumb mode. arm core_state arm resume 0x104040 ``` HTH, -- Jonathan Brandmeyer PlanetiQ _______________________________________________ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
