Hi, This post is the start of the process to formally define the tiers for RTEMS. The RTEMS Tiers helps the project and you understand the current tested state of RTEMS in an open and public manner. It is important we do this and we get valid results.
Up to this starting I have made a bit of guess at the structure and now is the time to create the tiers based on real results. This is needed so we can move to cutting a 5.1(?) release. The tiers are defined here: https://docs.rtems.org/branches/master/user/hardware/index.html#tiers. The current tier structure can be viewed here: https://git.rtems.org/rtems-tools/tree/tester/rtems/rtems-bsps-tiers.ini To be placed in a tier there needs to be test results posted to bu...@rtems.org. The archive of recent test results can be viewed here: https://lists.rtems.org/pipermail/build/2017-October/date.html I encourage everyone to run the tests and add `--mail` to the `rtems-test` command line and post results. If you need a hand doing this or there are problems please ask. Notes ----- 1. We need to examine the current failures, timeouts and invalid test results and either fix or tag as expected failure. 2. Tier 4 architectures and BSP can be removed after the next release unless someone steps up and we can move the BSP to tier 3. 3. We will not or should not be changing tiers once a release branch is made. Tier 1 ====== BSP --- 1. xilinx_zynq_zedboard 2. beagleboneblack 3. pc686 Architecture ------------ 1. ARM (Cortex-A9, Cortex-A8) 2. Intel i386 (i686) Tier 2 ====== Empty (no posted test results, SPARC sim, ARM qemu anyone?) Tier 3 ====== All others. Tier 4 ====== BSP --- 1. epiphany_sim Architecture ------------ 1. Epiphany Thanks Chris _______________________________________________ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
