** Information type changed from Private to Public

** Description changed:

  [Description]
-   Support for Intel Staging Feature to allow staging microcode before 
bringing down the CPU to activate the new microcode. 
+   Support for Intel Staging Feature to allow staging microcode before 
bringing down the CPU to activate the new microcode.
  
  [Hardware Information]
-   Architecture:
-     Intel / AMD (x86_64)
-   Platform(s):
-     Granite Rapids
-     Sierra Forest
-   Date HW is expected at Canonical:
-     
-   Component(s):
-     Other
+   Architecture:
+     Intel / AMD (x86_64)
+   Platform(s):
+     Granite Rapids
+     Sierra Forest
+   Date HW is expected at Canonical:
+ 
+   Component(s):
+     Other
  
  [Software Information]
-   Target Version:
-     24.04
-   Target Kernel:
-     6.13
-   Commit IDs:
-     TBD
-   External Links:
-     
https://lore.kernel.org/lkml/[email protected]/
+   Target Version:
+     24.04
+   Target Kernel:
+     Landed in 6.19, request backport to 6.8
+   Commit IDs:
+     bffeb2fd0b9c x86/microcode/intel: Enable staging when available
+ 4ab410287bfd x86/microcode/intel: Support mailbox transfer
+ afc3b5095461 x86/microcode/intel: Implement staging handler
+ 079b90d4ba8d x86/microcode/intel: Define staging state struct
+ 7cdda85ed90c x86/microcode: Introduce staging step to reduce late-loading time
+ ed44a5625f30 x86/cpu/topology: Make primary thread mask available with SMP=n
+   External Links:
+     
https://lore.kernel.org/lkml/[email protected]/
  
  [Business Justification]
-   
  
  [Testing guidance]
-   
  
  [External ID]
-   LFE-547
+   LFE-547

** Changed in: intel
       Status: In Progress => Fix Released

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https://bugs.launchpad.net/bugs/2096965

Title:
  [GNR][SRF] microcode: seamless: MCU staging

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