Public bug reported:
Two interim SAUCE fixes on top of the already-merged CXL Reset v9 series (in
`26.04_linux-nvidia-bos`). Both harden the CXL Reset path around the CXL Device
DVSEC enable state.
These are stopgaps: both fixes are already included in CXL Reset v12 series not
yet integrated in 26.04_linux-nvidia-bos
- Patches
1. **cxl: Restore CXL Device DVSEC enable state** (`3836d203b290`)
Cache the CXL Device DVSEC control value alongside the early HDM snapshot,
restore the CXL.cache and CXL.mem enable bits after a PCI reset, and refresh
the cached value when the CXL core changes memory enablement.
*(drivers/cxl/core/pci.c, drivers/cxl/core/reset.c, include/cxl/cxl.h)*
2. **cxl: Require enabled cache for CXL Reset** (`61bd392aaefd`)
Check the live CXL Device DVSEC control state before exposing CXL Reset, and
require CXL.cache to be enabled in addition to the existing CXL.mem
requirement — capability bits alone do not indicate whether the protocols are
actually active.
*(drivers/cxl/core/reset.c)*
- Follow-up
When this tree is later refreshed to cxl-reset v12 or above, these two SAUCE
commits must be reverted — the equivalent changes land as part of v12, so
keeping them would duplicate/conflict with the refreshed series. Track them as
revert-on-refresh.
** Affects: linux-nvidia-bos (Ubuntu)
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/2167292
Title:
cxl: DVSEC enable restore and require cache for cxl reset
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