drm.debug=0xe capture attached (boot to failure, kernel 7.0.0-1009-oem
/ 7.0.12). Root failure is eDP link training, not PSR:
[drm:intel_dp_dump_link_status] ln0_1:0x0 ln2_3:0x0 align:0x0
sink:0x0 adj_req0_1:0x33 adj_req2_3:0x33
[drm:intel_dp_link_training_clock_recovery] Max Voltage Swing reached
[drm:intel_dp_link_train_phy] Link Training failed at
link rate = 810000, lane count = 4
[drm] *ERROR* Timed out waiting for DP idle patterns
No clock recovery on any lane. The same link trained successfully at
boot at the identical rate and lane count (t=12.4s, LINK_RATE_SET 07).
Failure occurs at t=5422s following a runtime panel power cycle
(intel_pps_on_unlocked "turn panel power on"). The external DP-4
display trained fine 90ms later at 540000/2, so this is eDP-specific.
Two apparent issues:
1) After training fails, i915 does not retry at a reduced link rate or
lane count. It proceeds directly to intel_enable_transcoder and
intel_edp_backlight_on, leaving a backlit panel on an enabled pipe with
no valid link - a black screen rather than a degraded-but-working mode.
2) The VBT does not identify this panel:
[drm:get_panel_type] Panel type (VBT): 255
[drm:get_panel_type] Selected panel type (fallback): 0
[drm:parse_lfp_data] Found panel mode in BIOS VBT legacy lfp
table: "640x480"
so eDP vswing/pre-emphasis and PPS parameters come from a
placeholder entry. Resulting PPS delays diverge sharply from spec:
bios power_up 1 backlight_on 1 backlight_off 1 power_down 500
power_cycle 5000
spec power_up 2100 backlight_on 500 backlight_off 500
power_down 5000 power_cycle 5100
-> panel power up delay 1, power down delay 50, power cycle 500
Is a 1ms power-up delay before link training plausible as the cause
of the clock recovery failure? Panel is AUO 0x2ea5, 3840x2400,
eDP DPCD 05 8b 87 04 1e.
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https://bugs.launchpad.net/bugs/2162145
Title:
i915: eDP-1 goes black after 2-3h uptime on ThinkPad P1 Gen 8 (Arrow
Lake-H, MTL display 14.00) - Timed out waiting for DP idle patterns
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