Public bug reported:
In order for the Serial ATS scheme on t254 to have greater than 512MB capacity
in the GMMU TLB cache:
- the GMMU must use 64kb or larger sized pages, and
- the SMMU must be able to provide a single SPA for the IOVA of a 64kb GMMU
page.
The SMMU can only satisfy that if:
- the OS uses 64kb sized pages, or
- the OS uses 4kb sized pages, but the SMMU stores 16 physically contiguous 4kb
pages, and sets the Contiguous Bit so that the SMMU recognizes that the 16
pages are contiguous.
The motivation is performance: without this support, we can only get good TLB
cache capacity on n1x with a 64kb pagesize kernel. With this patch, we can get
the same TLB cache capacity as 64k pagesize, but with 4kb pagesize in the
kernel.
** Affects: linux-nvidia-6.14 (Ubuntu)
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/2112600
Title:
IOMMU: Support contiguous bit in translation tables
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